Method for inserting an asynchronous 139,264 kbit/s signal into

Details Method for inserting an asynchronous 139,264 kbit/s signal into Method for inserting an asynchronous 139,264 kbit/s signal into

1989-04-17

1993-05-25

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 99, 370102, H04J 322

Patent

active

052146430

ABSTRACT:
A method for inserting an asynchronous 139,264 kbit/s signal into a 155,520 kbit/s signal interlaces an asynchronous 139,264 kbit/s signal from the European digital signal hierarchy into the frame structure of a 155,520 kbit/s signal STM-1 of a network node interface NNI. Bits that are compiled in the form of a virtual container VC-4 in a sub-frame are inserted into the frame structure, which sub-frame is composed of 9 sections each having respectively 261 sub-sections of 1 byte or, respectively, 8 bits each. The first sub-section is reserved for a path overhead (POH). The remaining 260 sub-sections are inventively subdivided into 20 blocks having a first part (W, X, Y, Z) of 1 byte for auxiliary signals and having a second part of 12 bytes composed of information bits (I). This method can be employed at a network node interface NNI in a synchronous digital hierarchy.

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Recommendation G. 754 entitled "Fourth Order Digital Multiplex Equipment Operating At 139,264 kbit/s and Using Positive/Zero/Negative Justification", pp. 167-169.
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