Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2006-03-21
2006-03-21
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S233100, C710S022000
Reexamination Certificate
active
07016213
ABSTRACT:
A host is coupled to a serially connected chain of memory modules. In one embodiment, a method for initializing the host and each of memory modules includes the host transmitting a first synchronization pattern and a second synchronization pattern downstream in response to a reset condition. The method also includes each memory module in the serially connected chain of memory modules receiving and forwarding the first and the second synchronization pattern. Each memory module receives and forwards the first and the second synchronization pattern. Further, the method includes the host transmitting a plurality of NOP packets downstream in response to transmitting the second synchronization pattern. Lastly, the method includes a portion of the memory modules injecting and transmitting NOP packets upstream in response to receiving the second synchronization pattern from downstream.
REFERENCES:
patent: 6781911 (2004-08-01), Riesenman et al.
patent: 2003/0179777 (2003-09-01), Denton et al.
La Fetra Ross V.
Miranda Paul C.
Reeves Richard W.
Advanced Micro Devices , Inc.
Ingrassia Fisher & Lorenz P.C.
Nguyen Dang T.
Nguyen Van Thu
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