Method for increasing the capacity of an integrated circuit...

Details Method for increasing the capacity of an integrated circuit... Method for increasing the capacity of an integrated circuit...

2002-04-16

2004-07-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C257S309000

Reexamination Certificate

active

06759305

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for increasing the capacity of an integrated circuit device. In particular, the present invention relates to a method for increasing the capacity of a DRAM (Dynamic Random Access Memory) using nanotubes, nanowires, or nanobelts.
2. Description of the Related Art
In prior art, a DRAM memory cell is composed of a transistor and a capacitor. With advances in technology, the size of a transistor has become smaller and smaller. But when the size of a transistor becomes smaller, the area of the capacitor electrode decreases. If the area of the capacitor electrode decreases, the capacity also decreases. However, in the DRAM memory cell, the capacity must high enough so as to maintain a predetermined voltage. Hence, in order to overcome the above problems, methods of increasing the surface area of the capacitor electrode to increase the capacity have been disclosed. This is generally accomplished by trenching and stacking. However, these methods require complicated processes so that the manufacturing cost cannot be reduced. increase the area of the capacitor electrode, the increase is still limited by photolithography limitations.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above-described disadvantages.
An object of the present invention is to provide a method for increasing the capacity of an integrated circuit (IC) device, including the steps of defining a catalyst area on a substrate, forming a nanotube, nanowire, or nanobelt on the catalyst area, forming a first dielectric layer on the nanotube, nanowire, or nanobelt and the substrate, and forming an electrode layer on the first dielectric layer.
According to above method of the present invention, the capacity is substantially increased by using the surface area of the nanotube, nanowire, or nanobelt as the area of the capacitor electrode without extending the original bottom area of the capacitor electrode. This successfully simplifies the process and decreases the manufacturing cost.


REFERENCES:
patent: 5973444 (1999-10-01), Xu et al.
patent: 6294450 (2001-09-01), Chen et al.
patent: 6448701 (2002-09-01), Hsu
patent: 6515325 (2003-02-01), Farnworth et al.
patent: 6542400 (2003-04-01), Chen et al.

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