Method for increasing system bandwidth through an on-chip addres

Details Method for increasing system bandwidth through an on-chip addres Method for increasing system bandwidth through an on-chip addres

1995-09-08

1997-03-25

Fears, Terrell W.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523001, 36518905, G11C 1300

Patent

active

056151675

ABSTRACT:
A computer system comprising one or more processor modules. Each processor module comprising a central processing unit comprising a storage element disposed in the central processing unit dedicated for storing a semaphore address lock value and a semaphore lock flag value, a cache memory system for storing data and instruction values used by the central processing unit, a system bus interface for communicating with other processor modules over a system bus, a memory system implemented as a common system resource available to the processor modules for storing data and instructions, an IO system implemented as a common system resource available to the plurality of processor modules for each to communicate with data input devices and data output devices, and a system bus connecting the processor module to the memory system and to the IO system.

REFERENCES:
patent: 5270975 (1993-12-01), McAdams
patent: 5426744 (1995-06-01), Sawase et al.

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