Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1999-09-20
2001-09-04
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S783000, C361S777000, C361S767000, C174S260000, C174S261000, C174S263000, C174S266000, C257S737000, C257S738000, C257S778000, C257S774000, C257S698000, C257S786000
Reexamination Certificate
active
06285560
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit devices. More specifically, the present invention relates to a method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package to increase the routability of the package substrate, and a BGA package so modified.
BACKGROUND OF THE INVENTION
The parallel drive towards total cost reduction and miniaturization has, in recent years, given rise to an increasing emphasis on very small IC package solutions. This is particularly evident in consumer based end equipment such as camcorders and mobile telephone handsets. Despite a formal definition, packages whose area is similar to that of the IC they encapsulate are loosely referred to as chip scale packages (CSPs).
CSPs are in many ways an ideal solution to the cost reduction and miniaturization requirement. They offer enormous area reductions compared with quad flat package, and have increasing potential to do so without adding system level cost. In the best case, CSPs are able to compete today, on a cost per terminal basis, with quad flat packages. For example, various CSPs from Texas Instruments are now available at cost parity with thin quad flat packages.
Texas Instruments produces a polyimide-based family of CSPs known as MicroStarBGA™ (see FIG.
1
). This CSP
10
, like most others, uses solder alloy balls
12
as the interconnection between the package substrate
14
and the board on which the packages is soldered. As with all such packages, the solder balls formed between the package and the board are susceptible to fatigue when exposed to cyclic ambient temperature conditions.
JEDEC and EIAJ are increasingly documenting fine pitch BGA industry standards. The finest pitch standard that is currently widely recognized is 0.50 mm pitch. However, broad acceptance and use of 0.50 mm pitch CSPs is still very limited, due to the following reasons:
1) Lack of package availability from a broad range of suppliers.
2) Lack of package reliability data, and concerns that reliability will not meet the requirements of even the consumer markets.
3) The printed circuit board (PCB) requirements for mounting such fine pitch packages are very demanding. There is limited availability of such boards, and in many cases, the higher PCB cost is prohibitive.
4) Lack of experience on the part of most SMT assembly operations in manufacturing with such fine pitch BGAs.
5) Belief that 0.50 mm pitch CSP component cost is inherently higher, on a cost per terminal basis, than for example, 0.80 mm pitch CSPs.
Clearly, key to the successful adoption of a package that has to meet the twin goals of system cost reduction and miniaturization, is the package reliability. As the ball pitch shrinks, it becomes more and more difficult to meet reliability specifications, due to the ball joint fatigue phenomenon mentioned in the introduction. Both the size (volume) and shape of the solder ball influence reliability. The weakest link in the system is normally the point of smallest cross-section in the solder joint, which is via (28), as seen in FIG.
2
.
Thus a major challenge in the design of the CSP substrate is to optimize the diameter of this solder via. However, as the ball density on the package increases (more balls on more rows, at finer pitch), substrate routing density also increases, often leading to a package design of inherent lower reliability. To demonstrate this, the current optimum design for reliability, as shown in
FIG. 3
, is:
Ball (12) pitch
500
um
Line (30)/Space
28/42
um
Via (32) diameter
280
um
Solder ball pad (34) diameter
380
um
NB pad size is via size + 100 um.
These optimum rules, based on design for reliability, allow only one trace or line (
30
) to pass between adjacent balls (
12
). This is important since in CSP packages, since a line or trace (
30
) must extend from each solder ball pad (
34
) to an exterior edge of the substrate (
14
) (e.g., to facilitate electrolytic plating). Such restriction of limiting one line or trace between adjacent balls will limit the total number of balls that may actually be implemented in a matrix type ball grid array since there will be a limitation on how many traces or lines may actually extend out to an exterior surface of the substrate.
FIG. 4
discloses a conventional ball footprint (regular pattern of 3 row of balls) having 144 balls (on a 0.5 mm pitch) on a 10×10 mm package body. To achieve this dense routing, a designer has to compromise. There are typically three options:
1) Tighten the line/space design rule for the connection traces. This can add cost or may be beyond the capability of the substrate technology. *
2) Reduce the via diameter. This will reduce the fatigue life of the solder joint.
3) Reduce the minimum overlap of the ball pad to via (see FIG.
4
). This has negative reliability implications, as it will effect the moisture sensitivity of the package.
* NB. The line/space design rules can be improved upon by reducing the copper film thickness. This will not be discussed since the principles explained here are applicable to enhance the package reliability for any given metal film thickness. The most common compromise, when faced with having to increase routing density, is to use the tightest line/space rule available for the given substrate technology, and then to reduce the ball via diameter. This is demonstrated in the example in
FIG. 5
, and is the design used for the footprint in
FIG. 4.
FIG. 5
discloses a routing pattern for 3 full rows of balls, in which:
Ball (12) pitch
500
um
Line (30)/Space
28/42
um
Via (32) diameter
218
um
Solder ball pad (34) diameter
318
um
Thus, in the case of
FIG. 4
(and by implication FIG.
5
), the designer chose option
2
. In order to allow two traces to route between adjacent balls, the via diameter had to be reduced from 280 um to 218 um, which is a violation of the optimum design rules which call for a via diameter of 280 um. There are significant reliability implications of such a modification or change, as is well known in the art.
SUMMARY OF THE INVENTION
A routing technique for improving device reliability by selectively depopulating solder balls (and their respective solder ball pads, vias and traces or lines) from a conventional foot print of a ball grid array (BGA) package, and a BGA package so modified. The routing technique uses the gap resulting from the depopulated solder balls as additional space for routing traces or lines from solder ball pads to an exterior surface of a substrate upon which a semiconductor die is mounted. An advantage of the present invention is that it permits the retention of an optimum via diameter while increasing the number of solder balls on ever shriking packages, thereby increasing device reliability.
REFERENCES:
patent: 5324985 (1994-06-01), Hamada et al.
patent: 5424492 (1995-06-01), Petty et al.
patent: 5491364 (1996-02-01), Brandenburg et al.
patent: 5729894 (1998-03-01), Rostoker et al.
patent: 5981873 (1999-11-01), Heo
patent: 6133134 (2000-10-01), Mehr
Brady III Wade James
Gaffin Jeffrey
Neerings Ronald O.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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