Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1998-12-02
2001-01-30
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S017000, C414S936000
Reexamination Certificate
active
06180424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of testing semiconductor wafers to locate problems resulting from the fabrication procedure.
2. Brief Description of the Prior Art
The fabrication procedure for fabrication of semiconductor devices generally requires several hundred steps. It is necessary that each step be repeatable and that all wafers fabricated during any step be subjected to the same conditions to the greatest extent possible in order to insure uniformity of device parameters within some predetermined window from wafer to wafer as well as to insure uniformity of parameters across a wafer.
In order to maximize such uniformity, a common technique for determining the process step responsible for a specific type of wafer to wafer parameter variation has been to process a lot of wafers through different pieces of equipment with the wafers being randomized in the loading cassette in order to randomize the order in which they are processed through various manufacturing equipments. Alternatively, wafers may be processed in a specific numeric order in specific equipments, different orders being associated with different pieces of equipment. The average parametric value or spatial variation of a parameter over the wafer is then correlated with the wafer processing sequence through each equipment in order to identify specific equipment for which the parametric variation sequence correlates with the processing order sequence. As part of this procedure, a unique readable number or bar code feature is provided on each wafer, the wafers are physically randomly rearranged from process step to process step or in some order less than every step, and the location of each wafer in the lot is read periodically by reading the readable number thereon and the location. A parameter or parameters are then checked afterwards for each wafer and correlated to the wafer order at each process step where wafers were randomized to determine any parameter differences from wafer process order and to determine how processing may have caused these parameter differences. While this method of randomizing the order of the wafers through various pieces of equipment is effective in isolating which piece of equipment is responsible for trends in the parameters from wafer-to-wafer within a lot, it does not help in determining which piece of equipment causes trends in parameters across a wafer such as a top of wafer to bottom of wafer variation or a left side of wafer to right side of wafer variation. To isolate the equipment causing this type of variation it is desirable to supplement the randomization of wafer processing order with a method to orient wafers at different angles before certain process steps so that it would be possible to explore variations in across-wafer parametrics as a function of different process steps. This has not been currently done in any systematic manner to date, such as by using specific or randomized rotational variations at designated process steps and then tracking the associated parametric variation on wafers. However, at present, there is no known procedure for automatically performing the function of wafer rotation in addition to the rearrangement of the wafer processing order with subsequent parametric tracking.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a procedure and system whereby wafers can not only be randomly rearranged in a lot being processed from process step to process step, but can also be rotated in accordance with a known pattern from process step to process step and be tracked automatically to determine the process step responsible for a specific type of across-wafer variation.
Briefly, the above is accomplished by providing a host computer which specifies wafer rotation instructions on a wafer by wafer basis either for predetermined lots in a specific test or for every lot at specified steps in the fabrication process. The host computer initially checks the equipment to ensure that it can accommodate rotated wafers. The host computer then downloads information to a sorter as to which wafers are to be rotated and the degree of rotation in addition to the random rearrangement of the wafers as performed in the prior art. The sorter orients the wafers in accordance with the information received from the host computer and sends the rotational information to a Wafer Sleuth computer or the like. The Wafer Sleuth computer finds parametric commonality to wafer orientation.
More specifically, a host computer is provided which controls the testing operation in accordance with the present invention. Initially semiconductor wafers are loaded into a cassette in standard manner for fabrication with the host computer tracking the location and rotational orientation of each wafer initially placed within the cassette. After one or more processing steps, as determined by the host computer, the wafers are rearranged within the cassette under control of the host computer with the host computer tracking the new location of each wafer within the cassette. Each wafer is also rotated within the cassette by a rotating tool under control of the host computer after one or more processing steps, such rotation being generally 90, 180 or 270 degrees for simplicity, though other angular arrangement are contemplated and can be used. Wafer rotation for each wafer is tracked by the host computer with such wafer rotation being concurrent with wafer rearrangement or independent of wafer rearrangement. Wafer rearrangement and wafer rotation can independently take place after each processing step or periodically according to programs set up in the host computer and can be concurrent or independent of each other. After all processing steps have been completed for wafer fabrication and the components on the wafer have been fabricated, one or more parameters of the fabricated components including components specifying spatial variation of a parameter measured with respect to the notch are tested in standard manner with the test results sent to the host computer on a wafer by wafer basis for correlation with the location and orientation of each wafer during processing to locate fluctuation of parameters from wafer to wafer in the fabrication process and to determine process locations or operations which may require correction.
REFERENCES:
patent: 5479108 (1995-12-01), Cheng
patent: 5511934 (1996-04-01), Bacchi et al.
patent: 5513948 (1996-05-01), Bacchi et al.
patent: 5698038 (1997-12-01), Guldi et al.
patent: 6021380 (2000-02-01), Fredriksen et al.
patent: 6027301 (2000-02-01), Kim et al.
Guldi Richard L.
Tigelaar Howard L.
Brady III Wade James
Picardat Kevin M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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