Fishing – trapping – and vermin destroying
Patent
1990-01-09
1992-04-21
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 49, 437 69, 437193, H01L 2176, H01L 21265
Patent
active
051067722
ABSTRACT:
A method for fabricating floating gate memory arrays with improved electrical erase characteristics and a reduced gate oxide defect density is described. According to the invented method, a protective polysilicon layer is deposited immediately following growth of the tunnel or gate oxide. The polysilicon layer caps the gate oxide--protecting it from exposure to defect-causing contaminants and to insure that a uniform tunnel oxide thickness is maintained across the entire length of the channel; especially over the electron tunneling regions. Following application of the protective polysilicon layer, a second polysilicon layer is deposited and merges with the first polysilicon layer to form the floating gate for the device. Erase speed is improved for flash EEPROM devices fabricated according to the present invention by about 5-100 times.
REFERENCES:
patent: 3984822 (1976-10-01), Simko et al.
patent: 4114255 (1978-09-01), Salsbury et al.
patent: 4178674 (1978-03-01), Liu et al.
patent: 4407696 (1983-10-01), Han et al.
patent: 4413403 (1983-11-01), Ariizumi
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4780424 (1988-10-01), Holler et al.
patent: 4816883 (1989-03-01), Baldi
patent: 4872041 (1989-10-01), Sugiura
patent: 5002898 (1991-03-01), Fritzinger et al.
patent: 5010028 (1991-04-01), Gill et al.
Isolation Process using Polysilicon Buffer Layer for Scaled MOS/VLSI, Y. Han, B. Ma Ext. Abstract 84-I, Journal of the Elec. Society, p. 98, 1974.
Hashi et al., "An improved LOCOS Technology using thin oxide and polysilicon buffer layers", J. of the Electrochemical Society of Japan, vol. 98, pp. 78-83, 1984.
Han et al., "Isolation process using polysilicon buffer layer for scaled MOS/VLSI", Proceedings VLSI science and technology, vol. 84-7, pp. 334-339, 1984.
Chaudhari C.
Hearn Brian E.
Intel Corporation
LandOfFree
Method for improving the electrical erase characteristics of flo does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for improving the electrical erase characteristics of flo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving the electrical erase characteristics of flo will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1585697