Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-27
2002-01-01
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C216S047000, C430S313000, C430S314000
Reexamination Certificate
active
06335260
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method for improving the dimple phenomena of a polysilicon layer. More particularly, the invention relates to a method for improving the dimple phenomenon of a polysilicon layer deposited on a trench consisting of a plurality of substantially T-shaped trench cells. Each of the substantially T-shaped trench cells includes a stick portion for accommodating a transistor cell and a bar portion for accommodating a gate bus.
BACKGROUND OF THE INVENTION
In advanced semiconductor integrated circuits (ICs), a trench structure is widely used to achieve various objectives. For example, the trench structure is used to form a deep trench capacitor whose capacitance increases with an increase in the longitudinal surface area of a dielectric so as to enlarge the integration of semiconductor ICs. Moreover, the trench structure is used to form a trench isolation for isolating semiconductor devices in semiconductor ICs so as to improve problems of the conventional LOCOS process such as the formation of so-called bird's beaks which occupy a larger amount of the surface area of the substrate, the occurrence of a less planar surface, and so on. In addition, the trench structure is also used to form a double diffused MOS transistor (DMOS), wherein a MOS transistor is formed within the trench, for applying high power ICs. With respect to the high power ICs, a trench consisting of a plurality of substantially T-shaped trench cells is usually employed because it is necessary to form many MOS transistors connected in parallel through out the trench. Each of the substantially T-shaped trench cells includes a stick portion for accommodating a transistor cell and a bar portion for accommodating a gate bus.
In a conventional method for manufacturing high power ICs, however, a serious dimple phenomenon typically occurs in a polysilicon film deposited on the trench consisting of the substantially T-shaped trench cells. Hereafter described in detail is the serious dimple phenomenon formed in the polysilicon film according to the conventional method for manufacturing the high power IC with reference to
FIG. 1
to FIGS.
5
(A) and
5
(B).
FIG. 1
is a cross-sectional view showing a semiconductor structure. FIG.
2
(A) is a plane view showing a conventional photomask pattern for forming a trench. Referring to
FIG. 1
, at first, a semiconductor substrate
1
such as silicon is prepared. Next, a pad oxide layer
2
made of silicon oxide, a silicon nitride layer
3
, and a mask oxide layer
4
made of silicon oxide are sequentially formed on the semiconductor substrate
1
by a conventional heat treatment or a chemical vapor deposition (CVD) process. Thereafter, a photoresist layer
10
is substantially uniformly coated on the mask oxide layer
4
. Subsequently, using a photomask with the conventional pattern shown in FIG.
2
(A), the photoresist layer
10
is exposed so as to transfer the photomask pattern into the photoresist layer
10
as a latent pattern. Then, the exposed photoresist layer
10
is developed to form a patterned photoresist layer (not illustrated).
In the conventional photomask pattern shown in FIG.
2
(A), the photomask pattern for forming a trench consists of a plurality of substantially T-shaped pattern cells
200
. Each of the substantially T-shaped pattern cells
200
includes a stick portion
201
and a bar portion
202
, in which the width
210
of the stick portion
201
is equal to the width
211
of the bar portion
202
. The bar portion
202
extends in a direction referred to as x while the stick portion
201
extends in another direction, referred to as y, being perpendicular to the x direction. Furthermore, the bar portion
202
has a first side
202
a
connected with the stick portion
201
, and a second side
202
b
located opposite to the first side
202
a.
Moreover, two adjacent T-shaped pattern cells
200
are connected at the respective bar portions
202
. As mentioned above, in the high power ICs, each of the stick portions
201
of the conventional photomask pattern for forming a trench is used to accommodate a MOS transistor cell, and the bar portions
202
are used to accommodate a gate bus, through which each of the MOS transistor cells is connected in parallel. It should be noted that although two rectangular corners are constructed at each of the intersections of the stick portions
201
and the bar portions
202
in the conventional photomask pattern shown in FIG.
2
(A), the developed patterned photoresist film is actually shown in FIG.
2
(B), and the condition shown is due to the effects of optical interference and diffraction during the exposure process. More specifically, each of the rectangular corners is dulled by the effects of optical interference and diffraction, and therefore the patterned photoresist layer after being developed, shown in FIG.
2
(B), has two rounded corners at each of the intersections of the stick poritons
201
and the bar portions
202
.
Subsequently, using the patterned photoresist layer as shown in FIG.
2
(B) as a mask, the mask oxide layer
4
, the silicon nitride layer
3
, the pad oxide layer
2
, and the semiconductor substrate
1
are selectively etched so as to form a trench
30
by the process of anisotropic dry-etching for example, plasma etching or reactive ion etching. FIG.
3
(A) is a cross-sectional view showing a structure of the trench, after the anisotropic etching, along a line A-A′ of FIG.
2
(B) while FIG.
3
(B) is a cross-sectional view showing a structure of the trench, after the anisotropic etching, along with a line B-B′ of FIG.
2
(B). Note that the patterned photoresist layer used as the mask has been removed in FIGS.
3
(A) and
3
(B).
Referring to FIGS.
4
(A) and
4
(B), as a gate oxide layer, a thin silicon oxide layer
5
is formed to cover the surface of the trench
30
. Next, the trench
30
is overfilled with a polysilicon layer
6
by the process of chemical vapor deposition. In addition, the deposited polysilicon layer
6
also covers the unetched surface of the mask oxide layer
4
. During the process of depositing the polysilicon layer
6
, a plurality of dimple lines
220
develop on the polysilicon layer
6
after a predetermined deposition period because the polysilicon layer
6
is deposited from the bottom surface and sidewalls of the trench
30
upwards, that is, from the edges of the trench pattern as shown in FIG.
2
(B). Each of the plurality of dimple lines
220
is substantially located along the symmetric center of the corresponding stick portion
201
or bar portion
202
. More specifically, with respect to stick portions
201
of the T-shaped trench cells, the polysilicon layer
6
is deposited from the sidewalls of the stick portions
201
upwards, as shown in FIG.
4
(A). Therefore, the dimple lines
220
are developed along the symmetric centers of the stick portions
201
after the completion of the depositing. With respect to the bar portions
202
of the T-shaped trench cells, similarly, the dimple lines
220
are developed along the symmetric centers of the bar portions
202
after the completion of the depositing, as shown in FIG.
4
(B). It should be understood that the dimple lines extending in the direction x intersect with the dimple lines extending in the direction y at dimple intersection points
221
. As compared with any other points of the dimple lines
220
, the dimple intersection points
221
are located the farthest from the sidewalls of the trench
30
. As a result, the deepest dimples are developed at the dimple intersection points
221
when the deposition of the polysilicon layer
6
is completed, as shown in FIG.
4
(B). In other words, the thickness of the polysilicon layer
6
in the vicinity of the dimple intersection points
221
is the thinnest. The dimple phenomenon at the dimple intersection points
221
causes several problems during the succeeding processes in such a way that it is impossible to fabricate the desired high power ICs.
These problems during the succeeding processes
Chang Su-wen
Chen Rong-ching
Lin Chin-lin
Tseng Mao-song
Bacon & Thomas PLLC
Blum David S.
Bowers Charles
Mosel Vitelic Inc.
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