Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2003-01-15
2004-06-08
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S145000
Reexamination Certificate
active
06747588
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of signal transformation for successive approximation for an analog-to-digital converter, and more specifically, to a method with increased resolution.
2. Description of the Prior Art
Recently, thanks to developments in computers, the world is entering the digital era. Videotapes, audiotapes and other analog data storage media are being gradually replaced by digital storage media, such as optical disks. Digital data can be processed by a computer system directly, so the application is more convenient. Generally speaking, analog signals require an analog-to-digital converter (ADC) to be transformed into digital signals. The most common ADC construction includes flash ADC, pipeline ADC and successive approximation ADC. Although flash ADC and pipeline ADC are faster than successive approximation ADC, their electricity consumption is also larger, and are not suitable for many systems with limited power supply.
Please refer to FIG.
1
.
FIG. 1
is a functional block diagram of a prior art successive approximation ADC
10
. The successive approximation ADC
10
comprises a comparator
12
, a control logic circuit
13
, a successive approximation register (SAR)
14
, and a digital-to-analog converter (DAC)
16
. The successive approximation register
14
comprises a digital bit stream
18
having a plurality of bits, such as a most significant bit (MSB)
20
and a least significant bit (LSB)
22
. The successive approximation register
14
referencing the digital value
18
will output a digital signal
24
to the DAC
16
, and then the DAC
16
will transform the digital signal
24
into an analog reference signal
26
. The comparator
12
will compare the analog reference signal
26
and an analog input signal
28
to form a comparison result
30
. For instance, if the analog reference signal
26
is larger than the analog input signal
28
, the comparison result
30
will be binary value “0”. On the contrary, if the analog reference signal
26
is smaller than the analog input signal
28
, the comparison result
30
will be binary value “1”. The control logic circuit
13
based on the comparison result
30
adjusts the digital value
18
stored in the successive approximation register
14
accordingly. As the digital value
18
changes, the digital signal
24
will also change and further influence the magnitude of the output analog reference signal
26
from the DAC
16
. This process will continue until the analog reference signal
26
approximates the analog input signal
28
and the least significant bit
22
of digital value
18
is set.
Please refer to FIG.
2
and FIG.
3
.
FIG. 2
is a block diagram of the DAC
16
shown in FIG.
1
.
FIG. 3
is a voltage level diagram of the analog reference signal
26
shown in
FIG. 1
The DAC
16
comprises a plurality of switches
34
a-d
, a plurality of first resistors
36
and a plurality of second resistors
38
. The resistance value (2R) of each first resistor
36
is twice the resistance value (R) of each second resistor
38
, and the method of electronic connection for the first resistor
36
and the second resistor
38
is a ladder-like architecture used as a voltage divider. Each switch
34
is used to select the voltage input for each first resistor
36
, such as a ground (GND) or an operational voltage (Vdd). In addition, every switch
34
maps to a corresponding bit of the digital value
18
, and if a bit has a binary value “1” in it, the corresponding switch
34
selects operational voltage Vdd. However, if a bit has a binary value “0” in it, the corresponding switch
34
selects ground GND. Please note, for easier illustration,
FIG. 3
only shows four switches
34
a-d
, and it is assumed that the bit length of digital value
18
is 4. Among them, switch
34
a
maps to most significant bit
20
, while switch
34
d
maps to the least significant bit
22
. A voltage level of output terminal A from the DAC
16
changes according to the voltage (Vdd or GND) at every switch
34
. If the digital value
18
is “1000”, switch
34
a
will connect to Vdd, while switches
34
b
,
34
c
, and
34
d
will all connect to GND. From the voltage divider circuit formed by resistors
36
and
38
, we know the voltage level of output terminal A is ½*Vdd. Similarly, if the digital value
18
is “0100”, the voltage level of the output terminal A is ¼*Vdd. If the digital value
18
is “0001”, the voltage level of output terminal A is ⅛*Vdd. If digital value
18
is “0000”, the voltage level of output terminal A is {fraction (1/16)}*Vdd. So if D
3
, D
2
, D
1
and D
0
represent digital values
18
from the most significant bit to the least significant bit respectively, by the superposition principle, we can conclude the following relationship between the voltage level Va of output terminal A and the digital value
18
:
Va
=(½
*D
3
+¼
*D
2
+⅛
*D
1
+{fraction (1/16)}
*D
0
)*(Vdd−GND)
By changing the bit value of digital value
18
, one can further adjust voltage level Va (the reference signal
26
shown in
FIG. 1
) at output terminal A of the DAC
16
. When the successive approximation ADC
10
starts operation, the successive approximation register
14
will set the most significant bit D
3
of the digital value
18
to be “1”, and the other bits D
2
~D
0
to be “0”.That is, the initial value of the digital value
18
is “1000”. So during a first pulse
40
a
, the voltage level of the analog reference signal
26
is ½*Vdd, as shown in FIG.
3
. The voltage level of the analog input signal
28
is greater than the analog reference signal
26
, so comparator
12
will transfer the result of comparison
30
into the successive approximation register
14
. Because the voltage level of analog reference signal
26
is smaller than analog input signal
28
, the successive approximation register
14
keeps the “1” in the most significant bit D
3
, and sets the next bit D
2
to “1”. Now the digital value
18
is “1100”. So during a second pulse
40
b
, the voltage level of the analog reference signal
26
is (½+¼)*Vdd. But, the voltage level of the analog input signal
28
is smaller than the analog reference signal
26
, so the comparator
12
will transfer the results of comparison
30
into the successive approximation register
14
. The successive approximation register
14
will reset bit D
2
to “0”, and set the next bit D
1
to “1”, now the digital value
18
is “1010”. During a third pulse
40
c
, the voltage level of the analog reference signal
26
is (½+⅛)*Vdd, and the voltage level of the analog input signal
28
is greater than the analog reference signal
26
, so the comparator
12
will transfer the result of comparison
30
into the successive approximation register
14
. As described, the successive approximation register
14
keeps the “1” in bit D
1
, and sets the next bit to “1”, and the digital value
18
becomes “1011”. Finally, during the fourth pulse
40
c
, the voltage level of the analog reference signal
26
is (½+⅛+{fraction (1/16)})*Vdd, and the voltage level of the analog input signal
28
is greater than the analog reference signal
26
, so the comparator
12
transfers the result of comparison
30
into the successive approximation register
14
. As described, the successive approximation register
14
keeps the “1” in bit D
0
. Since bit D
0
is the least significant bit, the successive approximation ADC
10
is finished one signal transformation process, that is, the analog input signal
28
is finally transformed into digital output signal
32
shown in
FIG. 1
(“1011”).
As described above, the successive approximation ADC
10
use the prior art binary search algorithm to detect voltage levels of the analog input signal
28
to produce the digital output signal
32
. For a successive approximation ADC
10
to transform an analog input signal
28
into a 4-bit digital output signal
32
, t
Huang Jia-Jio
Lin Yi-Ping
Faraday Technology Corp.
Hsu Winston
Wamsley Patrick
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