Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
1999-04-02
2002-08-27
Nguyen, Nam (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S102000, C205S104000, C205S123000, C205S157000
Reexamination Certificate
active
06440289
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor seed layers and more specifically to forming seed layers by electroplating.
BACKGROUND ART
In the manufacturing of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of the conductive material into the oxide layer and the semiconductor devices. A seed layer is then deposited on the barrier layer to form a conductive material base, or “seed”, for subsequent deposition of conductive material. Typically, the seed layer is used as one electrode for an electroplating process in which a conductive material is deposited over the barrier layer formed on the channel oxide layer and in the first channel openings. The conductive material is then subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin dielectric stop layer, or stop nitride layer, over the first channels and the first channel oxide layer. Subsequently, a via dielectric layer, or oxide layer, is deposited on the stop nitride layer followed by deposition of a thin via stop layer, or via nitride layer. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride.
A via step photoresist is used in a photolithographic process to designate round via areas over the first channels, and etches are performed through the second channel oxide layer and via nitride layer to position the vias. The via step photoresist is then removed, or stripped. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The second damascene step photoresist is then removed. A further nitride etch process removes the nitride above the first channels in the via areas. After the openings for the channels and vias are formed, a barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer by a process such as chemical vapor deposition. This is followed by an electroplating of the conductive material on the seed layer in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
In place of etching the metalization materials, the damascene technique and electroplating are used for depositing the metalization materials. In order for electroplating to successfully fill the required channels and vias, it needs good copper seed coverage. As the devices get smaller and smaller, the aspect ratio (i.e., the ratio of depth to width) of channel and/or via in the damascene structure is getting higher. This high aspect ratio is putting a severe constraint on copper seed coverage inside the small and tall features. Seed coverage is also important to insure successful filling during electroplating, especially for copper and copper alloy metalization materials.
In channels and vias with minimal copper seed coverage, the thickness of the seed varies at different parts of these features. Typically, the thickest coverage from non-electrochemical deposition occurs at the re-entrant, or top opening, of a feature. If a moderate to high plating rate electrochemical deposition process is employed to fill such a feature, the thicker seed at the top of this feature will have a much faster deposition rate. The bottom and sidewall near bottom will have a much slower deposition rate. This disparity in deposition rate is a result of three factors. First, the electric field at the re-entrant and top of the structure is stronger and results in faster deposition. Second, the greater abundance of copper ion at the re-entrant results in faster buildup. Third, thinner or insufficient seed at the bottom and bottom sidewall will develop a higher electrical resistance whereas the thicker seed at the top of the feature has a much lower electrical resistance which will effect the deposition rate.
In order to fill a feature properly, it is necessary to carefully balance the deposition rate at five different locations on the feature. These locations are the top surface, the re-entrant, the top sidewall, the bottom sidewall, and the bottom. It has been almost impossible to consistently achieve the desired balance and high aspect ratios have been subject to problems with voids forming in the features. These voids result in higher resistance and open circuit failures.
As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and higher aspect ratio channels and vias, it is becoming more pressing that solutions be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for forming a seed layer starting with a non-electrochemical deposition of an initial deposition of the seed layer. This is followed by a very slow deposition rate electrochemical deposition at the beginning of the plating process to overcome the initial thin seed coverage at the bottom and bottom sidewall of a feature. The electrochemical deposition is accelerated to a slightly faster rate to build up a thicker and more uniform seed layer at the bottom and bottom sidewall while an organic additive in the plating bath is used to reduce plating at the re-entrant and top surface. When the bottom and bottom sidewall meet, a much higher plating rate is used.
The present invention further provides a method for using deposition current and an organic additive to balance the deposition of the seed on the five critical areas of a semiconductor feature.
The present invention further provides a thin copper seed deposited at a very low deposition rate of about 1 to 15 angstroms per sec. of direct current which is applicable to small geometry and to high aspect ratio features, e.g., trench or via for single or dual damascene techniques. After the deposition of a few hundred (100 to 300) angstroms of copper seed, the deposition rate is increased to a low 30 to 40 angstroms per second until the bottom sidewall and bottom close. T
Mei-Chu Woo Christy
Rangarajan Bharath
Singh Bhanwar
Advanced Micro Devices , Inc.
Ishimaru Mikio
Leader William T.
Nguyen Nam
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