Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-11-05
2001-02-13
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S426000, C438S427000, C438S439000
Reexamination Certificate
active
06187650
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of forming isolation for integrated circuits, and more specifically, to a method of forming a planar silicon nitride layer for use in shallow trench isolation or DRAM trench capacitors.
BACKGROUND OF THE INVENTION
In the formation of integrated circuits, the manufacture of isolation structures between semiconductor devices for insulating purposes is crucial. In either ULSI or in VLSI, a tiny amount of leakage current can induce significant power dissipation for the entire circuit. Therefore, it is very important to form an effective isolation between semiconductor devices. In addition, with the trend towards higher density integration, effective isolation must be done in a smaller isolation space.
Presently, various isolation technologies have been proposed. These include LOCOS (LOCal Oxidation of Silicon) and shallow trench isolation (STI) technologies. The most widely used method for forming isolation regions is the LOCOS structure. The LOCOS structure involves the formation of Field OXides (FOX) in the nonactive regions of the semiconductor substrate. In the other words, the FOX is created on the portion of the wafer that is not covered by a silicon nitride/silicon oxide composition layer. Unfortunately, the surface topography of the FOX cannot meet the stringent space demands of submicron devices. Additionally, as device geometry reaches submicron size, conventional LOCOS isolation has a further limitation. Notably, the bird's beak effect causes unacceptably large encroachment of the FOX into the device active regions.
Trench isolation is one of the newer approaches adopted and is used primarily for isolating devices in VLSI and ULSI. Trench isolation can be considered as a replacement for conventional LOCOS isolation. As seen in
FIG. 1
, in the basic STI technology, a pad layer
103
is first formed on the semiconductor wafer
101
. The pad layer
103
may be formed by oxidizing a bare silicon wafer in a furnace to grow the pad oxide layer
103
of about 100 to 250 angstroms thickness. The pad oxide layer
103
is most typically formed from silicon dioxide.
Next, a furnace silicon nitride layer
105
of about 1500 to 2000 angstroms thickness is then deposited on the pad oxide layer. The silicon nitride layer
105
is used as a stop layer and is formed on the pad oxide layer
103
. Turning to
FIG. 2
, a masking and etching step is then performed to form trenches
201
about 0.4 to 0.5 &mgr;m in depth by anisotropically etching into the silicon wafer.
Next, an oxide is deposited onto the wafer. The oxide may be a CVD oxide or a high density plasma chemical vapor deposition (HDPCVD) oxide. Typically, the oxide
203
needs to be planarized using a chemical mechanical polishing (CMP) technique.
The use of silicon nitride in the formation of trenches is a common technique. Indeed, not only is silicon nitride used in the formation of trenches for STI, but also in the formation of trenches for DRAM trench capacitors.
It has been found that when performing the CMP process to planarize the oxide layer
203
, a within wafer variation in the planarity of the silicon nitride layer exists. In other words, the silicon nitride layer is not globally planar over an entire wafer. This is believed to be caused by prior steps in the manufacturing process. The variation in the silicon nitride level causes variation in the planarity of the STI structures, which can be a factor device threshold voltage (V
t
) variation.
Therefore, a need arises for an improved method of forming a silicon nitride layer that has high global planarity. The silicon nitride layer can then be used in the process of forming trenches for either STI or DRAM capacitors.
SUMMARY OF THE INVENTION
A method of forming a planar silicon nitride layer is disclosed. The method comprises: forming a pad oxide layer on said substrate; forming a first nitride layer on said pad oxide layer; forming a stop layer on said first nitride layer; forming a second nitride layer on said stop layer; performing intermediate processes that damage said second nitride layer; removing said second nitride layer; removing said stop layer such that said first nitride layer remains as said planar silicon nitride layer.
REFERENCES:
patent: 5360753 (1994-11-01), Park et al.
patent: 5783476 (1998-07-01), Arnold
patent: 5817568 (1998-10-01), Chao
patent: 5866466 (1999-02-01), Kim et al.
patent: 5894059 (1999-04-01), Peidous et al.
patent: 5910018 (1999-06-01), Jang
Chiu Sheng-Fen
Shiao J. S.
Wu Joseph
Blakely , Sokoloff, Taylor & Zafman LLP
Pham Long
ProMOS Tech., Inc.
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