Method for improving dielectric polishing

Details Method for improving dielectric polishing Method for improving dielectric polishing

2005-01-18

2005-01-18

Goudreau, George A. (Department: 1763)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S692000, C438S725000, C438S757000, C438S694000, C438S700000

Reexamination Certificate

active

06844237

ABSTRACT:
According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step514).

REFERENCES:
patent: 5738757 (1998-04-01), Burns et al.
patent: 5981353 (1999-11-01), Tsai

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