Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-09-17
2001-01-30
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S700000, C438S745000, C438S754000, C205S656000, C205S669000, C205S684000
Reexamination Certificate
active
06180526
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for forming a conductive layer on a semiconductor wafer. More particularly, the present invention relates to a method of forming a conductive layer on a semiconductor wafer of line width smaller than 0.18 microns.
2. Description of the Prior Art
In manufacturing semiconductor devices, the line width is getting smaller, thus the copper metallization will replace the aluminum to meet the RC delay requirement when a process of 0.18 micron or below is followed. Combining TaN and Cu for barrier layer and seed layer with the electroplating deposition is the main trend for the generation of a 0.18-micron process. However, the conformity of the barrier layer and the seed layer is a main issue in fabricating the semiconductor device especially when the process of 0.18 micron or below is utilized.
In some applications, the CVD (Chemical Vapor Deposition) Cu is utilized to fabricate the conductive layer in a semiconductor device to obtain the conformal step coverage, particularly when the line width is small. In general, the copper layer fabricated by CVD uses SF
3
containing chemistry as a source, so the resistivity of the resulting copper layer is high. Especially when the thickness of the copper layer is decreased, the resistivity of the copper layer will be increased. Furthermore, the residue after the CVD can create the problem of adhesion between the copper layer and the underlying layer, and the CVD technique is expensive. So the CVD technique suffers from the problems mentioned above, and the CVD technique is suitable for the seed layer of electrochemical deposition when utilizing Cu metallization in 0.18-micron or below process.
To overcome the adhesion problem and to avoid the increase of the resistivity of the Cu layer formed by CVD, the PVD (Physical Vapor Deposition) technique is used in Cu metallization. As shown in
FIG. 1
, a semiconductor wafer includes a contact hole
10
in the dielectric layer
11
on the substrate
12
, and the PVC technique is used to form a barrier layer
15
on the topography of the semiconductor wafer. Generally, the barrier layer
15
is formed of Ta, TiN or TaN. Because the nature of the PVC technique, the overhang
19
is formed in the barrier layer
15
at the corner
17
of the dielectric layer
11
.
Before filling the contact hole
10
with copper, a seed layer
20
composed of copper as shown in
FIG. 2
is formed on the barrier layer
15
. When the seed layer is formed by the PVD technique, the overhang
21
of the seed layer
20
is also formed on the overhang
19
of the barrier layer
15
. Even though the seed layer
20
is formed by a ECD (Electrochemical Deposition) technique. Because the current density on the surface of the overhang
19
is greater than the other portion of the barrier layer
15
, the deposition rate of copper at the overhang
19
is higher than the other portion of the barrier layer
15
. Accordingly, the overhang
21
of the seed layer
20
is formed at the overhang
19
, and the conformity of the seed layer
20
is poor even though the electrochemical deposition is utilized.
Because of the overhang formed by the PVD technique, it is very difficult to fill copper in the contact hole. This is particularly true when the 0.18-micron process or below is utilized, in which case the opening of the contact hole may be closed, and the failure of the formation of a via plug may result. A cheap technique that can fabricate a conformal seed layer without the issue of adhesion is necessary in the process of 0.18-micron or below.
In the other respect, the chemical mechanical polish (CMP) is often used to polish the surface of the semiconductor wafer to reduce the altitude difference of the surface of the semiconductor. Yet the higher surface and the lower surface are simultaneously polished during the CMP process. So the resulting planarity is not good enough, thus the planarity of the semiconductor wafer can be further improved by another method.
SUMMARY OF THE INVENTION
One preferred embodiment of the present invention provides a method for improving the conformity of the copper conductive layer in a contact hole. Thus a plug can be formed in the resulting contact hole without void formation in the plug. The aforementioned method includes the following steps. First, immerse the conductive layer of the semiconductor wafer into an electrolyte. The first portion of the conductive layer at the opening of the contact hole is in contact with the electrolyte, the conductive layer in the contact hole is not in contact with the electrolyte due to the surface tension of the electrolyte. Next, electrically couple the electrolyte to the cathode of the source power. Finally, electrically couple the conductive layer to the anode of the power source. Thus the first portion of the conductive layer at the opening of the contact hole is removed to improve the conformity of the copper conductive layer.
In the other preferred embodiment of the present invention, a method for improving the planarity of a conductive layer on the semiconductor wafer is presented. The method mentioned above includes the following steps. First, immerse the conductive layer into an electrolyte. The conductive layer includes the first portion and the second portion, and the second portion of the conductive layer is thinner than the first portion of the conductive layer. The first portion of the conductive layer is in contact with the electrolyte, and the second portion of the conductive layer is not in contact with the electrolyte due to a surface tension of the electrolyte. Subsequently, electrically couple the electrolyte to the cathode of a source power. Finally, electrically couple the conductive layer to an anode of the power source until the electrolyte is in contact with the second portion of the conductive layer.
REFERENCES:
patent: 4978639 (1990-12-01), Hua et al.
patent: 5723028 (1998-03-01), Poris
patent: 5985125 (1999-11-01), Kim
Harness & Dickey & Pierce P.L.C.
Industrial Technology Research Institute
Kunemund Robert
Umez-Eronini Lynette T.
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