Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-06-24
2001-07-24
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S624000, C438S626000, C438S634000, C438S697000, C438S760000
Reexamination Certificate
active
06265315
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to fabricating integrated circuits on semiconductor substrates, and more specifically to a method for making planar interlevel dielectric (ILD) layers with improved uniformity across the substrate using an improved chemical/mechanical polishing and etch-back technique. This method results in a more uniform ILD layer over the rough metal topography, thereby allowing the etching of contact openings or via holes to a uniform depth for improved contact resistance control.
(2) Description of the Prior Art
As the circuit density on Ultra Large Scale Integration (ULSI) circuits increases, it becomes necessary to increase the number of metal interconnecting levels to effectively wire up the discrete semiconductor devices on the semiconductor chips. In the conventional method, the different levels of metal interconnections are separated by insulating layers, commonly referred to as interlevel dielectric (ILD) layers. Via holes or contact holes are etched in the ILD layers to connect one level of metal to the next, or to make electrical contacts to the underlying polysilicon or polycide lines. These multilevels of metal interconnections generally lead to a rough topography. This makes it difficult to form the patterned photoresist layers having high-resolution, distortion-free images over this rough topography, and is due to the shallow depth of focus (DOF) necessary for exposing the photoresist. Also anisotropic plasma etching (directional etching) is used in conjunction with these photoresist masks to pattern the electrically conducting layers to achieve the closely spaced metal lines having high aspect ratios. Therefore it is difficult to pattern the metal over the rough topography without leaving residue that can cause intralevel electrical shorts. This problem becomes more severe as the circuit density increases and the minimum feature sizes are further reduced in size.
Therefore, it is common practice in the semiconductor industry to use planarizing techniques for leveling the ILD layers over the patterned metal layers to eliminate the rough topography. Several methods of planarizing the ILD layers include using a low-flow-temperature glass such as borophosphosilicate glass (BPSG), which is reflowed. Another method is to deposit a spin-on glass (SOG) which is then cured to provide a planar SiO
2
layer. Other methods of planarizing are to deposit a photo-resist layer and etching back the photoresist layer and the ILD layer using a plasma etch having a 1:1 etch-rate selectivity. However, because of loading effects during etching which are area dependent it is difficult to maintain a 1:1 etch-rate ratio.
More recently, chemical/mechanical polishing (CMP), which provides a global planarization across the substrate, has attracted much interest in the industry. This CMP is achieved in a polishing tool using a polishing pad and a polishing slurry containing an abrasive material (e.g., alumina or silica). During polishing a chemical etchant is generally introduced to remove material from the wafer by both chemical and mechanical means. However, there are several drawbacks to CMP. For example, one of the drawbacks is that it is difficult to control the polishing uniformity across the substrate. This large variation in ILD thickness across the substrate makes it difficult to reliably etch submicron contact openings or via holes in the ILD layer at the different chip (die) locations across the wafer. This variation in thickness results in contacts or vias having large differences in aspect ratio (height/width of opening). This difference in aspect ratio results in large variations in contact resistance (R
c
) across the wafer from die to die, and makes it difficult to control the tolerance of the electrical design parameters.
Several methods for planarizing an insulating layer over patterned metal layers have been reported. For example, Nakano et al., U.S. Pat. No. 5,532,191, describe a method for forming a planar silicon oxide by chemical/mechanical polishing. A conformal silicon oxide layer is deposited over the metal lines and a thinner insulating layer having a slower polishing rate is deposited. The convex portions of a conformal silicon oxide layer over the metal lines is polished to the thinner insulating layer in the concave portions between the metal lines, as shown in
FIGS. 1A-1D
of Nakano's patent, and the polishing is stopped to provide a planar surface. Another method for forming planar insulation-filled trenches in a silicon substrate is described by Venkatesan et al., U.S. Pat. No. 5,459,096. The trenches are filled with a conformal dielectric layer which is then patterned. A thin second planarization layer is deposited, and the structure is chemical/mechanically polished back to the second planarizing layer resulting in a planar trench-filled structure. Sune et al. in U.S. Pat. No. 5,332,467 utilize polishing-stop islands formed in the recesses of the rough surface. An insulating layer is deposited and polished back to the polishing-stop islands to provide a planar surface. Pramanik et al. in U.S. Pat. No. 5,399,533 describe a method for planarizing a spin-on glass layer using an underlying silicon nitride etch-stop layer, and Morita in U.S. Pat. No. 5,540,811 planarizes an insulating layer by depositing a silicon nitride polish-back stop layer. The silicon nitride layer is patterned to leave portions in the concave areas, and then the insulating layer is polished back to the polish-back stop layer to provide a planar surface.
However, there is still a current need for providing a more planar interlevel dielectric (ILD) layer on integrated circuits that allows contact openings or via holes to be etched more controllably to a constant etch depth across the substrate.
SUMMARY OF THE INVENTION
It is therefore a principal object by a first embodiment of the present invention to provide a novel CMP/etch-back method for planarizing an interlevel dielectric (ILD) layer with improved ILD thickness over the underlying metal topography across the semiconductor substrate.
It is another object by a second embodiment of the present invention to provide a novel CMP/etch-back method for planarizing an interlevel dielectric (ILD) layer with improved ILD thickness over the underlying metal topography across the semiconductor substrate, and having a low-dielectric-constant (low-k) insulator in the recesses of the patterned electrically conducting layer.
Still another object of this invention is to provide an etch-stop layer with high etch selectivity to reduce the non-uniformity across the substrate resulting from the chemical/mechanical polishing, thereby providing a more controllable contact or via hole etching tolerance.
A further object of this invention is to provide a simple cost-effective manufacturing process.
In accordance with the objects of this invention, a new method for forming a planar interlevel dielectric (ILD) layer that is uniformly thick across the substrate is described. A semiconductor substrate is provided having a patterned electrically conducting layer, such as polysilicon, polycide, or metal. The patterned conducting layer is used for electrically connecting the devices on the substrate. The method of forming a planar ILD layer over the patterned conducting layer begins by depositing a conformal first insulating layer having a uniform thickness across the wafer. A conformal etch-stop layer, such as silicon nitride (Si
3
N
4
), is then deposited over the first insulating layer. A second insulating layer, composed of silicon oxide (SiO
2
), as described in a first embodiment, or a low-dielectric-constant insulator, as described in a second embodiment, is deposited to a thickness that is greater than the thickness of the patterned conducting layer. The second insulating layer is then chemically/mechanically polished (CMP) back to within a few thousand Angstroms (1000-2000 Angstroms) of the etch-stop layer. The remaining second insulating layer is then selectively etche
Lee Yu-Hua
Wu James (Cheng-Ming)
Ackerman Stephen B.
Guerrero Maria
Meier Stephen D.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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