Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Magnetic field
Reexamination Certificate
2000-11-18
2002-08-06
Chaudhuri, Olik (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Magnetic field
C438S003000, C438S240000, C365S173000
Reexamination Certificate
active
06429497
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to magnetic tunnel junctions such as spin dependent tunneling (“SDT”) junctions. The present invention also relates to information storage devices such as Magnetic Random Access Memory (“MRAM”) devices.
A typical MRAM device includes an array of memory cells, word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
In one type of MRAM device, each memory cell includes an SDT junction. The magnetization of an SDT junction assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’ The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction is a first value (R) if the magnetization orientation is parallel and a second value (R+&Dgr;R) if the magnetization orientation is anti-parallel. The magnetization orientation of a SDT junction and, therefore, its logic state may be read by sensing its resistance state.
The SDT junctions can be shorted by electrostatic discharge, handling errors (during manufacture) and circuit anomalies such as voltage spikes. Each shorted SDT junction can cause a bit error.
In a resistive cross point array that does not use switches or diodes to isolate memory cells from one another, a shorted SDT junction can also render other memory cells in the same column and row unusable. Thus, a single shorted SDT junction can cause column-wide and row-wide errors as well.
When data is read back from the MRAM device, error code correction may be used to recover data from a complete rows and columns of unusable SDT junctions. However, correcting a thousand or more bits in a single column or row is costly, both from a time standpoint and a computational standpoint. Moreover, an MRAM device is likely to have more than one shorted SDT junction.
If an MRAM device contains too many unusable SDT junctions, that device is rejected at the manufacture stage. Thus, electrostatic discharge, handling errors and circuit anomalies can reduce manufacturing yield.
It would be desirable to prevent damage resulting from handling errors and circuit anomalies. It would also be desirable to prevent damage resulting from electrostatic discharge. However, prevention against electrostatic discharge is expensive and difficult to implement.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a magnetic tunnel junction includes a tunnel barrier having base material that is partially processed (e.g., underoxidized, undernitrided). The partially processed base material substantially increases breakdown voltage of the junction. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.
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Blum David S
Chaudhuri Olik
Hewlett--Packard Company
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