Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-01-25
2001-11-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S244000, C438S253000, C438S387000, C438S638000, C438S675000, C438S723000, C430S316000, C430S317000
Reexamination Certificate
active
06319789
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to integrated circuits and more particularly to a capacitor having improved surface area for use in an integrated circuit and a method for forming the same.
BACKGROUND OF THE INVENTION
Capacitors are used in a wide variety of semiconductor circuits. Capacitors are of special concern in DRAM (dynamic random access memory) memory circuits; therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in any other type of memory circuit, such as an SRAM (static random access memory), as well as in any other circuit in which capacitors are used.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
10
. For each cell, one side of the storage capacitor
14
is connected to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1” signal) of the circuit. The other side of the storage capacitor
14
is connected to the drain of the access field effect transistor
12
. The gate of the access field effect transistor
12
is connected to a signal referred to as the word line
18
. The source of the field effect transistor
12
is connected to a signal referred to as the bit line
16
. With the circuit connected in this manner, it is apparent that the word line controls access to the storage capacitor
14
by allowing or preventing the signal (a logic “0” or a logic “1”) on the bit line
16
to be written to or read from the storage capacitor
14
.
The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors which are stacked, or placed, over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the invention will be discussed in connection with stacked capacitors but should not be understood to be limited thereto. For example, use of the invention in trench or planar capacitors is also possible.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) having an oval or circular cross section. The wall of each tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric. A preferred dielectric is tantalum pentoxide (Ta
2
O
5
). The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a conductive plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material later in the fabrication process). The sidewall and closed end of the tube form a container; hence the name “container capacitor.” Although the invention will be further discussed in connection with stacked container capacitors, the invention should not be understood to be limited thereto.
The electrodes in a DRAM cell capacitor must be conductive, and must protect the dielectric film from interaction with interlayer dielectrics (e.g., BPSGS) and from the harsh thermal processing encountered in subsequent steps of DRAM process flow. For example, Ta
2
O
5
dielectrics may be used for high density DRAMs, such as 64 Mbit and 256 Mbit DRAMs, because chemical vapor deposition (CVD) of Ta
2
O
5
provides a high dielectric constant (about 20-25) and good step coverage.
Several methods have been attempted to increase capacitance, including depositing HSG inside a container capacitor together with a smooth polysilicon deposited on the outside of the container, depositing a smooth metal on both the inside and outside of the capacitor, and depositing a double sided HSG. However, these prior methods require additional process steps which deviate from the standard IC fabrication process.
SUMMARY OF THE INVENTION
The present invention has advantages over the previous methods in that capacitor has improved surface area by eliminating the plug connection to the active area and additionally forming a portion of the capacitor in a second BPSG layer. By eliminating the plug connection and forming a portion of the capacitor in a second BPSG layer over the area where the plug was, the present invention provides a fabrication process and capacitor structure that achieves high storage capacitance with a modified standard fabrication process without increasing the frequency of capacitor defects or the size of the capacitor. The present invention provides a capacitor formed by an improved process and etchback of the polysilicon plug to form a capacitor structure that achieves high storage capacitance, and, has the configuration shown, for example, in FIG.
2
. The improved capacitor has a first lower section formed in a first BPSG layer
142
having a width x and a second upper section formed in a second BPSG layer
148
having a width y which is greater than width x. By forming the capacitor in a second section, the present invention increases the capacitance of the device by modifying the standard IC fabrication process and without requiring time consuming and costly processing.
REFERENCES:
patent: 5401681 (1995-03-01), Dennison
patent: 5854119 (1998-12-01), Wu et al.
patent: 6027984 (2000-02-01), Thakur et al.
patent: 6037213 (2000-03-01), Shih et al.
patent: 6042999 (2000-03-01), Lin et al.
patent: 6077790 (2000-06-01), Li et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Lytle Craig P.
Micron Techonology, Inc.
Smith Matthew
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