Method for improved alignment for semiconductor devices with bur

Details Method for improved alignment for semiconductor devices with bur Method for improved alignment for semiconductor devices with bur

1988-01-06

1990-06-26

Hearn, Brian E.

Metal treatment

Barrier layer stock material, p-n type

With contiguous layers of different semiconductive material

148DIG102, 148 332, 437 90, 437924, H01L 2912, H01L 2930

Patent

active

049369300

ABSTRACT:
A method is provided to improve the alignment process in fabricating an integrated circuit with buried layers. The buried layers are implanted in a substrate and driven in, but without the usual step at their perimeter. A target pattern is etched into the substrate surface by means of plasma-assisted etching. An isotropic epitaxial layer is then grown at reduced pressure over the substrate surface so that the target is replicated on the epitaxial layer surface. The target as replicated is thus suitable for optical alignment, either manually or by automatic alignment equipment.

REFERENCES:
patent: 4125418 (1978-11-01), Vinton
patent: 4256829 (1987-03-01), Daniel
patent: 4503334 (1985-03-01), King et al.
patent: 4572765 (1986-02-01), Berry
patent: 4639798 (1987-01-01), Drake et al.
Ghandhi, VLSI Fabrication Principles, John Wiley & Sons, New York, 1986, pp. 475-517.

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