Method for implementing synchronous pipeline exception recovery

Details Method for implementing synchronous pipeline exception recovery Method for implementing synchronous pipeline exception recovery

1988-07-20

1989-10-17

Smith, Jerry

Boots, shoes, and leggings

3642318, 3642421, 3642476, 3642563, 371 12, G06F 938

Patent

active

048751600

ABSTRACT:
Pipelined CPUs achieve high-performance by fine tuning the pipe stages to execute typical instruction sequences. Atypical instruction sequences result in pipeline exceptions. The disclosed method provides graceful exception handling and recovery in a micropipelined memory interface. The use of a memory reference restart command latch allows an implementation that requires no additional logic for conditional writing of states pending exception checking. The exception handling hardware is minimized because instructions which cause exceptions are never re-executed, and exception handling microcode executes in-line with the normal microcode flow.

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patent: 4701844 (1987-10-01), Thompson et al.
patent: 4707784 (1987-11-01), Ryan et al.
patent: 4750112 (1988-06-01), Jones et al.
patent: 4794518 (1988-12-01), Mizushima
patent: 4794524 (1988-12-01), Carberry et al.
patent: 4794527 (1988-12-01), Stewart et al.

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