Multiplex communications – Wide area network – Packet switching
Patent
1995-03-10
1996-10-29
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 60, 370 61, H04L 1252, H04L 1254
Patent
active
055703585
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a method for implementing switching in the time domain, and to a method for implementing switching in the space domain, for signals of several different levels of hierarchy, the signals having a common frame structure. An example of such a frame structure is the frame structure of an STM-1 signal used in the SDH system; this frame structure will be illustrated in greater detail below.
The method of the invention can thus be used in both time and space switches. In this connection, the term time switch refers to a device capable of switching the contents of any time slot in the frame structure of an incoming signal to any time slot in an outgoing frame structure (switching in time). In addition to a time switch, this device can also be called a time slot interchanger. The term space switch, in turn, refers to a switch capable of connecting any incoming line to any outgoing line (switching in space).
In known switching methods, the switching of e.g. the tributary unit groups (TU-12, TU-2, TU-3) of an STM-1 frame is implemented by giving switching instructions separately to 3, 21 or 63 columns by starting the switching from column 13 on TU-3 level and from column 19 on TU-2 and TU-12 levels. It has thus been possible to effect the switching on one level at a time. Another way has been to switch columns 19 to 270 in blocks of 63 columns, and to give switching instructions separately to columns 13 to 18 on the TU-3 level. In this way it has been possible to effect cross-connection on all three of the levels at the same time.
The drawback of the known switching methods is, however, that, in practice they entail fairly complicated equipment.
SUMMARY OF THE INVENTION
The object of the present invention is to remedy the drawback described above.
The idea of the invention is to utilize the frame structure of an incoming signal by defining a basic switching block, which recurs in the frame structure in the same form from the point of view of switching, and to effect the switching of all time slots merely on the basis of an address control memory intended for the switching of the basic switching block by reading the said memory cyclically, and by skipping the switching instructions at the time slots which are not cross-connected.
Owing to the solution of the invention, it is not necessary to inform the actual switch about the level of the signals to be cross-connected. The solution thus allows the practical equipment to be implemented in a more simplified manner than before.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following, the invention will be described in more detail with reference to the examples which are based on an STM-1 signal and illustrated in the attached drawings, in which
FIG. 1 shows the basic structure of a single STM-N frame,
FIG. 2 shows the structure of a single STM-1 frame,
FIG. 3 shows the assembly of the STM-N frame from existing PCM systems,
FIG. 4 shows an STM-1 frame and blocks of different sizes contained in it,
FIG. 5 shows a time switch and implementation of time switching according to the invention,
FIG. 6 is a more detailed view of the read unit of the time switch shown in FIG. 5,
FIG. 7A and 7B show how the switching instructions of the address control memory in the time switch of the invention are distributed to the different channels in three separate cases,
FIG. 8 shows how the switching instructions of the address control memory in the time switch of the invention are distributed to the channels of different levels of hierarchy in a case where signals of three different levels of hierarchy are switched simultaneously, and
FIG. 9 shows a solution of the invention as applied to a space switch.
DETAILED DESCRIPTION
FIG. 1 illustrates the structure of an STM-N frame used in the SDH network, and FIG. 2 illustrates a single STM-1 frame. The STM-N frame comprises a matrix with 9 rows and N.times.270 columns so that there is one byte at the junction point between each row and the column. Rows 1-3 and rows 5-9 of the N.times.9 fi
REFERENCES:
patent: 4320501 (1982-03-01), Le Diev et al.
patent: 4471479 (1984-09-01), Waas
patent: 5197063 (1993-03-01), Nakano et al.
patent: 5311506 (1994-05-01), Beisel
Alatalo Hannu
Kokko Marko
Blum Russell
Nokia Telecommunications Oy
Olms Douglas W.
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