Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
1999-06-11
2001-09-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Reexamination Certificate
active
06291305
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to integrated semiconductor circuits. More particularly, the present invention relates to an on-chip method for implementing resistors, capacitors and inductors in an integrated circuit using vertical stack vias and interconnects.
BACKGROUND OF THE INVENTION
An integrated circuit, sometimes referred to as a chip, an IC, or semiconductor device, is an intricate microscopic map of transistors and other microscopic components programmed along electrical interconnections. The transistors and other microscopic components are formed on a silicon substrate, while the electrical interconnections, are typically formed layer by layer on the semiconductor substrate.
Using techniques well known in the art of semiconductor fabrication, transistor elements and other devices are fabricated on the silicon substrate. The transistors are then connected by interconnects which could be poly silicon and metals. The combination of these transistors and interconnects forms the integrated circuit on the silicon substrate. Typically, the integrated circuit will include a plurality of electrical interconnections which are arranged in a pattern. Often, due to limited spacing requirements, this pattern will require overlapping traces. On a single flat surface, it is impossible to implement this trace pattern and so conductive layers are disposed in an overlapping pattern as necessary separated by insulators.
The metal layers are typically composed of aluminum or aluminum compounds and represent the electrical interconnections between the components which are formed on the silicon substrate. These metal layers are separated from other conductive layers and devices formed on the silicon substrate by an interlevel dielectric isolation (ILD) layer. This ILD layer typically includes silicon dioxide.
The metal layers are connected to one another, and to regions on the silicon substrate, by use of conductive holes which are formed perpendicular to the substrate and are commonly known as “vias”. These vias arc microscopic column shaped openings which are formed to join metals on different layers. The vias are filled with a conductive material such as aluminum or refractory metal such as tungsten. An outermost passivation layer protects the underlying layers of the integrated circuit. Typically, the outermost passivation layer is formed using chemical vapor deposition techniques well known in the art of integrated circuit fabrication.
Often, resistance, capacitance and/or inductance is needed in a circuit, including an integrated circuit. This can be accomplished in an integrated circuit by fabricating on-chip resistors or capacitors in the integrated circuit or providing off-chip resistors, capacitors and inductors. To the extent that inductance is possible on a conventional integrated circuit, the inductance is that associated with the field built around a single trace.
FIG. 1
shows a planarized schematic view of a prior art integrated circuit which includes a resistor
202
and a capacitor
208
. The integrated circuit includes a silicon substrate
200
, upon which multiple devices (not shown). To form the resistor
202
a pattern can be formed, the dimensions of the pattern in relation to the sheet resistance of the structure, which is conventionally specified in units of ohms per square (&OHgr;/□), represents the resistance of the structure. Accordingly, the resistance of such a pattern is directly proportional to the length of the trace or the number of squares in the trace. Depending upon the desired resistance of the structure it can be formed of metal, doped silicon, doped polysilicon and can be formed using techniques well known in the art of semiconductor fabrication. However, attainable values of sheet resistance are such that resistors in the kilo ohm range and higher require lengthy patterns containing many squares. The large area need for implementing the horizontal serpentine pattern of a high-value resistor is a practical limitation in an integrated circuit.
In the prior art, a capacitor
208
is implement as schematically shown in
FIG. 1
in reference to two parallel planes
201
and
205
. Each plane
201
and
205
contains a metalization layer or surface
204
and
207
. The metals
204
and
207
are separated by an insulator. The capacitor
208
may conventionally frequently range from 1 nF to 100 nF and may occupy an area of perhaps 1.5 by 2.5 mm, however the actual value will be a function of the area of the parallel plates
204
and
207
in relation to their relative spacing from one another as is well known. In one typical integrated circuit process, parallel metalization levels are separated by a distance of approximately 1.5 microns. Because capacitance in a parallel plate capacitor is directly proportional to the size of the plates and inversely proportional to the distance between the plates, designs requiring high capacitance will require larger parallel metal plates and are, accordingly, often difficult to implement given the spacial limitations within the integrated circuit.
Preferably, resistors and capacitors are designed in a fully planarized fashion as illustrated by FIG.
1
. The individual elements are set out in a horizontal plane with spacing allocated to the various elements on the plane. Accordingly, the layout of these on-chip resistors and capacitors requires the use of significant space within the integrated circuit. In complex integrated circuits, such as very large scale integration (VLSI) circuits, maximization of efficient use of spacing is often difficult to achieve. Accordingly, what is needed is a method for implementing resistance and/or capacitance within an integrated circuit while maximizing efficient use of spacing within the integrated circuit.
Additionally, prior art implementation of an inductor within an integrated circuit has been severely limited. Inductance is typically accomplished by mounting a separate coiled inductor exterior to the integrated circuit and connecting the inductor to the integrated circuit through metal leads. Alternatively, a thick short medullization layer was implemented on one of the planes above the silicon substrate in order to mimic both resistive and inductive properties within the integrated circuit. Unfortunately, neither of these methods provides for an effective inductor within an integrated circuit. Accordingly, what is further needed is a more efficient method for designing inductance within an integrated circuit while minimizing spatial requirements required for implementing such a design.
SUMMARY OF THE PRESENT INVENTION
The present invention is for a method of vertically implementing on-chip resistance, capacitance and/or inductance using stacked vias and metalization layers within the integrated circuit. Column shaped openings or vias are formed within the integrated circuit and connect from a silicon substrate to various metal traces. The vias are filled with conductive material such as tungsten. Parallel vias are used to form capacitance, while multiple vias and metal traces are arranged in various patterns over several planes in order to form resistance and/or inductance. The use of the stacked vias and metal traces in a vertical fashion reduces lateral spacing required to implement on-chip resistance, capacitance and/or inductance and allows for more efficient use of space in very large scale integration.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in more detail, in conjunction with the accompanying drawings.
REFERENCES:
patent: 5874770 (1999-08-01), Saia et al.
patent: 5936298 (1999-08-01), Capocelli et al.
Huang Chi-Jung
Li Ken Ming
Peng Helen
Carr & Ferrell LLP
Hoang Quoc
Nelms David
S3 Graphics Co., Ltd.
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