Amplifiers – With semiconductor amplifying device – Including frequency-responsive means in the signal...
Reexamination Certificate
2001-08-08
2004-02-24
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including frequency-responsive means in the signal...
C330S292000, C327S359000, C360S046000
Reexamination Certificate
active
06696896
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to amplifier circuits and more particularly to amplifier circuits that relate to magnetic storage systems.
BACKGROUND OF THE INVENTION
The trend in the data storage industry is to continuously increase the data rate at which information is read from magnetic storage surfaces such as disk drives. Designers are developing high performance disk drives which tend to have magnetic domains positioned close together on the magnetic storage media, creating a high density of data recording. Additionally, these drives have greater rotation rates than lower performance drives, resulting in higher data rates. Higher data rates require faster voltage transitions at the input to the channel circuitry used to read data from the disk surface. Faster voltage transitions produce higher frequency components in the voltage input signal, thereby requiring a greater bandwidth from the channel circuitry.
Until recently, designers primarily used inductive heads to read data from these disk surfaces. Unfortunately, inductive heads are limited in the bandwidth at which they may function. Designers, accordingly, developed magnetoresistive (MR) heads which do not have the large inductance associated with previous heads. These MR heads, therefore, can accommodate higher data rates. Data is read from a disk surface by monitoring the changing resistivity of the MR head. The resistance of MR heads is a function of the strength of the magnetic field to which it is exposed. Since the resistance of the head varies with magnetic flux, the current through, or the voltage across the head is a function of the data written on the magnetic media.
This approach to reading information from the surface of a disk drive has proven to be very successful. However, as higher performance storage systems are developed, there is a continuing demand for greater bandwidth from the head and the read circuitry associated with the head. The ability to attain greater bandwidths is currently limited by the response of the MR head and the preamplifier used to generate read signals. However, these problems are not limited to preamplifiers used with disk drive systems. The problem is seen throughout the field of amplifiers. Amplifiers with greater bandwidth are desired.
Referring to
FIG. 1
, the traditional circuit for implementing programmable poles and zeros in preamplifiers usually uses a series of MOSFET circuits which is illustrated as MOSFET switches
102
-
116
, which are MOSFETS acting as switches, connected in series with capacitors
132
to
146
respectively.
FIG. 1
illustrates a zero circuit
150
and a pole circuit
162
. The pole circuit
162
is connected to load resistors
160
and
162
while the zero circuit
150
is connected to the degeneration resistor
164
. The circuit of
FIG. 1
works adequately for low frequencies, however problems develop for preamplifiers having a frequency of 2 Gb per second and requiring a bandwidth in excess of 1 GHz with programmable poles ranging from several hundred MHz to over 1 GHz and zeros ranging from several hundred MHz to over 2 GHz. The parasitics of the switches
102
-
116
dramatically limit the performance of the programmable poles and zeros at the higher frequencies. More specifically, the size the MOSFET switches
102
-
116
are conflicting with respect to the characteristic trying to be emphasized. In the on state, the characteristic desired from these MOSFET switches is low on resistance by making these MOSFET switches larger. While in the off state the characteristic desired from these MOSFET switches is low parasitic capacitance by making these MOSFET switches smaller. These two desired characteristics are in conflict. These characteristics include unintended peaking or roll off. More particularly, sizing of the gate width is important depending on whether the switch is either in the on or off state. In the on state, when the switch is activated to connect the voltage V
cc
with the capacitor C
132
to
146
to the AC ground, it is desirable that the width of the MOSFET switch
102
-
116
be large to reduce the on resistance of the specific MOSFET so that the capacitor
132
-
146
can be effective and produce the desired amplitude of peaking (zeros) or roll off (poles). Furthermore, when the MOSFETs
102
-
116
are in the off state, the switches
102
-
116
isolate the non-amplifier side of the capacitor from AC ground by the high impedance of switches
102
-
116
, the width of the MOSFET drain of the switch should be small to reduce the parasitic capacitance of the MOSFET. The small parasitic capacitance is desired so that the unintended peaking or the roll off does not occur. It is illustrated that the MOSFET switch and more particularly the drain to source is in the current path of the above described capacitors.
As can be appreciated from the above discussion, no single MOSFET switch size can produce both satisfactory peaking or roll off amplitude when the MOSFET switch is on and satisfactory absence of unintended peaking or roll off when the MOSFET switch is off. Therefore, the MOSFET switch in the current path with the capacitor is not a feasible method of implementing programmable poles and zeros in preamplifiers as it introduces parasitic capacitance at the drain and prevents the preamplifier from achieving the required performance, especially at high frequencies.
SUMMARY OF THE INVENTION
The present invention eliminates a switch with high parasitic capacitance in the current path with the capacitor between the amplifier and AC ground. The present invention uses a variable impedance device with variable impedance which is controlled by a current source to set the impedance.
REFERENCES:
patent: 3643184 (1972-02-01), D'Alessandro
patent: 4050023 (1977-09-01), Edgar
patent: 4458212 (1984-07-01), Brehmer et al.
patent: 4634986 (1987-01-01), Brookshier
patent: 5406220 (1995-04-01), Jones, III et al.
patent: 5581495 (1996-12-01), Adkins et al.
patent: 5633765 (1997-05-01), Lin et al.
patent: 5642079 (1997-06-01), Whiteside
patent: 5673003 (1997-09-01), Zocher
patent: 5760641 (1998-06-01), Granger-Jones et al.
patent: 6342813 (2002-01-01), Imbornone et al.
Brannon Craig M.
Kuehlwein Jeremy
Brady W. James
Choe Henry
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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