Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2006-08-29
2009-06-30
Chambliss, Alonzo (Department: 2892)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S109000, C029S857000, C257S772000
Reexamination Certificate
active
07553696
ABSTRACT:
A method and structure are provided for implementing component placement suspended within electrical pin grid array packages for enhanced electrical performance. A solder column grid array is coupled between a printed circuit board and a first level package. A component is connected between a predefined pair of adjacent columns in the solder column grid array suspended between the printed circuit board and the first level package.
REFERENCES:
patent: 4734818 (1988-03-01), Hernandez et al.
patent: 6320249 (2001-11-01), Yoon
Bartley Gerald Keith
Becker Darryl John
Dahlen Paul Eric
Germann Philip Raymond
Maki Andrew Benson
Chambliss Alonzo
International Business Machines - Corporation
Pennington Joan
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