Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Software program
Reexamination Certificate
1999-12-14
2004-01-13
Lim, Krisna (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Software program
C703S024000, C703S025000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06678646
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to programmable logic devices formed on integrated circuits, and more specifically to a method of implementing a physical design for a dynamically reconfigurable logic circuit.
BACKGROUND ART
Dynamically reconfigurable logic, also known as Cache Logic, is a digital design technique for reconfiguring programmable logic circuits such as SRAM-based Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Dynamically reconfigurable logic exploits the dynamic and partial reconfigurability of SRAM-based FPGA's by reconfiguring part of the FPGA logic while the remainder of the logic continues to operate uninterrupted.
The concept of dynamically reconfigurable logic is illustrated in
FIG. 6
, which shows reconfiguration of a portion of the logic implemented on an FPGA. The replacement logic
120
is stored in an off-chip memory
124
. During reconfiguration, only that portion of the logic to be replaced, reconfigurable logic
116
, is overwritten. All other logic, static logic
114
and unused logic
112
, is unaffected and continues normal operation. The configuration bitstream size is minimized since only a portion of the FPGA is reconfigured.
Consequently, both the time taken to reconfigure the FPGA, called the reconfiguration latency, and the off-chip storage size are minimized. This contrasts with traditional FPGA design that results in a fixed-logic implementation of a circuit that does not change at run-time.
Since FPGA resources are shared between a number of different implementations of a logic circuit, Dynamically Reconfigurable Logic provides designers with important benefits. Less FPGA resources are used than would result from a fixed-logic design. This can be exploited to pack more logic into a given FPGA or to use fewer or smaller, less-expensive FPGAs than would otherwise be possible. Consequently, cost, board-area and power consumption can all be reduced. In addition, in a system-wide context, Dynamically Reconfigurable Logic provides a level of run-time flexibility normally associated with microprocessors together with operating speeds and fine-grain parallelism approaching those of custom hardware. This benefit has been exploited by reconfigurable computing applications that use FPGAs to implement application-specific, custom co-processors whose function can be changed at run-time.
Commercially available Computer Aided Design (CAD) tools provide a good solution for traditional, fixed-logic FPGA design. A designer can specify the logic, perform functional simulation, create a physical layout, perform post-layout simulation, and generate an FPGA configuration bitstream. The result of this is that the designer can proceed to the prototype stage with a high degree of confidence in the FPGA design. As part of this process, automatic FPGA compilation (floorplanning, placement and routing) methods provide fast design turn-around and the designer need not be concerned with the details of the target FPGA architecture or have expert-knowledge of the FPGA manual place and route methods.
For Dynamically Reconfigurable Logic design existing, commercial, physical design methods have serious limitations. In order to use these methods, a designer must develop each different context of the FPGA logic independently, as a fixed-logic design. The incremental design change capability provided by most FPGA vendors can be of assistance in this process by allowing designers to make changes in the physical layout without altering the placement and routing of static logic. For designs that have many possible variants for sections of logic, this procedure is extremely time consuming and difficult to manage. Furthermore, floorplanning, placement and routing of design changes must be performed manually to ensure that the same FPGA resources are used by different contexts. This requires that the designer be thoroughly intimate with the details of the target FPGA architecture and is an expert-user of the physical design methods.
For early practitioners of new technology, the limitations of the present physical design methods may be tolerable. However, for the majority of designers, who have time-to-market pressures and may not possess detailed knowledge of FPGA architectures and methods, the present physical design methods are not acceptable. In order to address this problem, it is necessary to integrate design methodology into the existing FPGA design flow as transparently as possible, to address the verification of the behavior of a Dynamically Reconfigurable Logic design, and to provide automation of the physical design process.
Prior attempts to solve this problem include U.S. Pat. No. 5,781,756 to Hung which discloses a dynamically and partially reconfigurable FPGA which allows run-time reconfiguration without having to rewrite entirely the configuration memory cells. The '756 patent also discloses a method for dynamically and partially reconfiguring the FPGA configuration without having to rewrite entirely the configuration cells. A memory configuration device is included in the FPGA for controlling the loading of the data register and address register of the FPGA. This device allows the skip over of unchanged configuration memory cells. Therefore, only the configuration cells that need to be changed will be rewritten.
A conference paper entitled “Automating Production of Run-Time Reconfigurable Designs” by Nabeel Shirazi, Wayne Luk, and Peter Y. K. Cheung discloses the matching of two successive circuit configurations to locate the components common to them, so that reconfiguration time can be minimized. The matching procedure contains three steps: 1) Representing the components in the two successive circuits as nodes in a bipartite graph; 2) computing the best match for each node in one configuration with a node in the other configuration, taking into account the values of the weights; 3) inserting RC-Mux and RC_Dmux to produce a combined circuit with explicit reconfigurable regions. However, in the overall design process, this matching occurs before the physical design process.
It is the object of the present invention to provide designers with a method for implementing the physical design for a dynamically reconfigurable logic circuit that provides a level of automation enjoyed in traditional, fixed-logic design.
It is a further object of the invention to provide a method of implementing a physical design that ensures that the implementation of the design is correct, that does not violate any electrical rules in the target device, and will protect against run-time contention for FPGA resources.
SUMMARY OF THE INVENTION
The above objects have been achieved by a method for implementing the manual and automatic physical design of dynamically reconfigurable logic applications. The method is carried out using software that forms a physical design flow to take a design specification from a schematic or high-level description language (HDL) through to FPGA configuration bitstream files. The method involves reading a design net list that includes a set of static macros and a set of reconfigurable macro contexts, compiling each of the reconfigurable macros, placing and routing an initial device context containing the set of static macros and the initial macro context for each of the reconfigurable macros, updating the device context by arbitrarily selecting a context for each reconfigurable macro, placing and routing the updated device context and repeating the updating and placing steps until all of the reconfigurable macro contexts have been placed and routed. Then, after the compilation process is complete, full, partial and incremental bitstreams are generated.
The method of the present invention frees designers from FPGA-specific considerations and allows them to focus on system level issues. No expert level knowledge of dynamic reconfigurable logic implementation or FPGA architecture is required to use the present invention, as the invention uses industry-standard design entry formats. Since ma
Dasari Ajithkumar V.
Mason Martin T.
McConnell David A.
Atmel Corporation
Lim Krisna
Phan Thai
Schneck Thomas
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