Method for I/O device layout during integrated circuit design

Details Method for I/O device layout during integrated circuit design Method for I/O device layout during integrated circuit design

1998-04-17

2000-05-02

Bowers, Charles

Semiconductor device manufacturing: process

With measuring or testing

H01L 2166

Patent

active

060571691

ABSTRACT:
A method for laying out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion. Also provided is a method for laying out pads for input/output (I/O) cells on an integrated circuit die in which size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.

REFERENCES:
patent: 4745305 (1988-05-01), Crafts
patent: 5155065 (1992-10-01), Schweiss

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