Method for high speed programming of a charge trapping...

Details Method for high speed programming of a charge trapping... Method for high speed programming of a charge trapping...

2007-04-30

2009-02-03

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185240, C365S185260

Reexamination Certificate

active

07486567

ABSTRACT:
A method of high speed programming and erasing of a charge trapping memory using turn-on-mode assist-charge (TOM-AC) operations. The charge trapping memory includes a charge trapping structure overlying a substrate body with source and drain regions. The charge trapping structure includes a charge trapping layer overlying a dielectric layer. The charge trapping layer has an assist charge site (also referred to as AC-site, AC-side, or a first charge trapping site) and a data site (also referred to as data-side or a second charge trapping site). Initially, to place the charge trapping memory cell in a TOM operation, both the AC-site and the data site of the charge trapping memory cell are erased to a negative threshold voltage level, −Vt, by FN injection, thereby inducing a hole charge induced channel between the source and drain regions.

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Yeh, et al., “PHINES: a novel low power program/erase, small pitch, 2-bit per cell flash memory” Electron Devices Meeting, 2002. IEDM '02. Digest. International Dec. 8-11, 2002 pp. 931-934.

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