Fishing – trapping – and vermin destroying
Patent
1993-07-15
1996-03-26
Breneman, R. Bruce
Fishing, trapping, and vermin destroying
437939, H01L 21324, H01L 21477
Patent
active
055020100
ABSTRACT:
A method of processing a semiconductor substrate includes the step of subjecting a semiconductor substrate to a heat treatment under a gaseous atmosphere. The method comprises the step of subjecting a semiconductor substrate to a high temperature heat treatment at temperatures not lower than 1100.degree. C. under a non-oxidizing atmosphere, wherein heat treatments before the high temperature heat treatment applied to the semiconductor substrate are applied under heat treating temperatures and heat treating time which fall within a region defined by a line connecting four points of (900.degree. C., 4 minutes), (800.degree. C., 40 minutes), (700.degree. C., 11 hours) and (600.degree. C., 320 hours) in a graph, in which the heat treating temperature is plotted on the abscissa and the heat treating time is plotted on the ordinate of the graph.
REFERENCES:
patent: 3925107 (1975-12-01), Goula et al.
patent: 3997368 (1976-12-01), Petroff et al.
patent: 4116719 (1978-09-01), Shimizu et al.
patent: 4220483 (1980-09-01), Cacgarra
patent: 4314595 (1982-02-01), Yamamoto et al.
patent: 4376657 (1983-03-01), Nagasawa et al.
patent: 4505759 (1985-03-01), O'Mara
patent: 4547256 (1985-10-01), Gurtler et al.
patent: 4548654 (1985-10-01), Tobin
patent: 4597804 (1986-07-01), Imaoka
patent: 4622082 (1986-11-01), Dyson et al.
patent: 4626450 (1986-12-01), Tani et al.
patent: 4637123 (1987-01-01), Cazcarra et al.
patent: 4666532 (1987-05-01), Korb et al.
patent: 4681983 (1987-07-01), Markvart et al.
patent: 4713354 (1987-12-01), Egawa et al.
patent: 5009926 (1991-04-01), Fukada
patent: 5094963 (1992-03-01), Hiraguchi et al.
patent: 5096839 (1992-03-01), Amai et al.
patent: 5286658 (1994-02-01), Shirakawa et al.
patent: 5327007 (1994-07-01), Imura et al.
patent: 5385115 (1995-01-01), Tomioka et al.
patent: 5403406 (1995-04-01), Falster et al.
patent: 5445975 (1995-08-01), Gardner et al.
Appl. Phys. Lett., vol. 46, No. 5, pp. 516-518, Mar. 1, 1985, Kenji Nishi, et al., "Fast Shrinkage of Oxidation-Induced Stacking Faults in Silicon at the Initial Stage of Annealing in Nitrogen".
Kobayashi Hideyuki
Nadahara Souichi
Terasaka Kunihiro
Yamabe Kikuo
Yamamoto Akihito
Breneman R. Bruce
Kabushiki Kaisha Toshiba
Whipple Matthew
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