Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-02-20
2004-08-03
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S426000, C438S453000
Reexamination Certificate
active
06770541
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to forming isolation regions in semiconductor substrates.
2. Background Art
In a Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) process, deep trench isolation regions are typically formed to provide isolation between adjacent active regions of a semiconductor substrate. A deep trench isolation region may electrically isolate, for example, a bipolar transistor, such as a silicon-germanium heterojunction bipolar transistor, from an adjacent CMOS transistor, such as a PFET, fabricated on the same semiconductor substrate. Deep trench isolation regions may be formed on a substrate after formation of, for example, field oxide isolation regions, a buried layer, and an epitaxial layer of silicon.
In a typical conventional deep trench isolation process, a layer of silicon nitride (“nitride”) is deposited on a silicon substrate at a thickness of approximately 1500 Angstroms, for example. A hard mask having an approximate thickness of 4500 Angstroms and comprising densified tetraethylorthosilicate (“TEOS”) oxide or high-density plasma (“HDP”) oxide is then formed over the nitride layer. A photoresist mask is formed and patterned over the hard mask, and a trench is etched to a depth just below a field oxide region. After removal of the photoresist mask, the trench is further etched into the silicon substrate to a depth of between approximately 7.0 and 10.0 microns. During trench etching, the hard mask is also etched, which results in a reduction in hard mask thickness by approximately one half. After performance of cleaning and other preparatory steps as known in the art, a densified TEOS oxide liner is formed on the sidewalls of the trench and on the surface of the silicon substrate. The TEOS oxide liner may have a thickness of approximately 1000.0 Angstroms or greater.
Next, in the conventional deep trench isolation process discussed above, a conformal layer of polycrystalline silicon (also referred to as polysilicon) is deposited over the silicon substrate and trench. The layer of polysilicon is then recess etched in the trench to a depth of approximately 1500.0 Angstroms below the interface of the field oxide region and the nitride layer. The hard mask situated over the layer of nitride is then removed in a wet etch process utilizing a buffered oxide etchant (“BOE”). However, since the polysilicon is recess etched to a depth of approximately 1500.0 Angstroms below the nitride layer, the BOE wet etch causes severe lateral etching of the field oxide region situated on the sidewalls of the trench.
In an attempt to reduce the severe field oxide lateral etching discussed above, semiconductor manufacturers have utilized a dry etch in place of the BOE wet etch. However, mainly as a result of non-uniformity in hard mask thickness resulting from etching of the hard mask during trench formation, the dry etch approach causes formation of a non-uniform “mini-trench” or cavity on either side of the polysilicon-filled trench. As a result, removal of the hard mask utilizing either the BOE wet etch or the dry etch approach causes undesirable deep mini-trenches or cavities to be formed in the field oxide.
Another approach utilizes a chemical-mechanical-polishing (“CMP”) step after polysilicon deposition to remove the hard mask. However, the CMP approach is a costly approach that is limited in application to shallow trench isolation technology.
Thus, there is a need in the art for an effective method for removing a hard mask in a deep trench isolation process.
SUMMARY OF THE INVENTION
The present invention is directed to method for hard mask removal for deep trench isolation and related structure. The present invention addresses and resolves the need in the art for an effective method for removing a hard mask in a deep trench isolation process.
According to an exemplary method for removing a hard mask in a deep trench isolation process in one embodiment of the present invention, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. The hard mask may be formed over a layer of nitride situated over the substrate, for example. The hard mask may be, for example, densified TEOS oxide and HDP oxide. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and a second sidewall. The trench may be formed by forming a photoresist mask on the hard mask, etching a trench to an initial depth, removing the photoresist mask, and etching the trench to a final depth, for example.
According to this exemplary embodiment, the hard mask is removed after forming the trench. The hard mask may be removed by, for example, etching the hard mask in an anisotropic dry etch process, where the anisotropic dry etch process is selective to nitride and silicon. Next, an oxide liner is deposited by a CVD process on the first and second sidewalls of the trench and over the substrate after the hard mask has been removed. The oxide liner may be densified TEOS oxide, for example. The oxide liner may be removed using a wet strip process, for example. According to one embodiment, the invention is a structure that is achieved by utilizing the above-described method. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
REFERENCES:
patent: 4871685 (1989-10-01), Taka et al.
patent: 5106777 (1992-04-01), Rodder
patent: 5306940 (1994-04-01), Yamazaki
patent: 5348906 (1994-09-01), Harajiri
patent: 6406972 (2002-06-01), Norstrom et al.
Kalburge Amol
Yin Kevin Q.
Cao Phat X.
Doan Theresa T.
Farjami & Farjami LLP
Newport Fab LLC
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