Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-05-29
2003-02-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S108000, C438S109000, C438S110000, C438S111000, C438S113000, C438S115000, C438S118000, C438S122000, C438S125000
Reexamination Certificate
active
06514790
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the parallel handling of a plurality of circuit chips. More particularly, the present invention relates to a simultaneous parallel handling of a plurality of circuit chips by a plurality of pick up devices.
2. Description of Prior Art
The development of contact and non-contact chip cards as well as of non-contact electronic labels has lead to a completely new and rapidly growing market for electronic micro systems with new requirements. Integrated circuits are no longer only installed in large devices or hand systems, but in a “bare” form in chip cards or electronic labels. At present electronic labels as the so-called “throw away electronics” mark the end of this development. This throw away electronics needs cheap chips and integrated circuits respectively. In order to make cheap chips of this kind feasible, special methods for a cheap larger scale production are necessary.
A cheap large scale production will only be feasible, if a parallel manufacture of a plurality of circuit chips in interconnected wafers can be carried out as long as possible. Thus, the integrated circuit contained in a circuit chip is usually completed while the circuit chip is still arranged in the interconnected wafers together with other circuit chips.
Only after the completion of the integrated circuits are the wafers separated into the individual circuit chips.
After the semiconductor wafer has been separated into the individual circuit chips, i.e. diced, they have to be handled in order to be positioned in their final destination, that is on the circuit substrate. After dicing the circuit chips, they are usually still arranged in a pseudo wafer arrangement on an auxiliary substrate. The term pseudo wafer arrangement means that the circuit chips are still positioned in the arrangement and distance of the original wafer, but separated from one another by dicing gaps. When further processed, one individual circuit chip after the other is usually separated from the auxiliary substrate by a pick device and handled for further processing by the pick device.
JP 10041695 A and the associated Patent Abstracts of Japan, Vol. 1998, No. 06, Apr. 30, 1998, explains a chip handling device which comprises a pick up head, which includes a plurality of pick up nozzles with a fixed spatial relation to one another. The pick up head can move freely to move the chips to and to fix the chips in a fixing position.
JP 10107490 A shows a device for the simultaneous picking up of several circuit chips, wherein the device comprises a pick up head with a plurality of pick up nozzles. According to this document, a position relation between the nozzles is recorded by a first camera, while a position relation of chips to be picked up is observed by a second camera. If the result of these observations is that all the pick up nozzles are arranged within a range of tolerance of the chips which guarantees correct picking up of the chips, they are picked up by a simultaneous up-and-down motion of the individual pick up nozzles. However, if the result of this observation is that one of the nozzles is not located within the range of tolerance of a respective chip, then only those chips whose pick up nozzles are located within the range of tolerance are picked up simultaneously. The nozzle which is not located within the range of tolerance is then spatially adjusted by a horizontal motion in order to reach the range of tolerance of the chip to be picked up. After the nozzle has been adjusted, this chip is picked up independently.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a method permitting parallel treatment of circuit chips even after dicing some out of the wafer.
This object is achieved by a method for the parallel handling of a plurality of circuit chips which are arranged in a first arrangement, which corresponds to the arrangement in the original wafer, on the surface of an auxiliary carrier. In a first step a plurality of circuit chips are picked up by a plurality of pick up devices. Then the plurality of pick up devices with the picked up circuit chips are moved to one or several carriers in such a way that, simultaneous with this motion, the first arrangement of the circuit chips is changed into a second arrangement which is different from the first arrangement simultaneously. Then the circuit chips are placed on the one or several carriers simultaneously.
The first arrangement of the circuit chips preferably defines first distances between the circuit chips, while the second arrangement determines second distances between the circuit chips, wherein the first distances are smaller than the second distances. Any device which is appropriate for holding a circuit chip can be used as a pick up device, wherein, e.g., a magnetic clutch, an electrostatic clutch or a vacuum clutch can be used. In addition pick up devices which are provided with an adhesive layer can be used. The individual circuit chips are preferably separated from the auxiliary carriers by adding energy to the joint between the auxiliary carrier and the circuit chip.
The carrier or the carriers the circuit chips are fixed on can be another auxiliary carrier or the circuit substrates which the circuit chips are to remain on for their final destination respectively. If the carriers are the circuit substrates, the circuit chips, simultaneously with positioning of the circuit chips on the circuit substrates, can be flip-chip bonded to these circuit substrates, e.g. by heating the pick up devices. Other methods of bonding or adhering can also be applied.
Thus the present invention eliminates disadvantages of the prior art, where the circuit chips are subjected to an individual processing after they have been separated or diced from one other. Thus, the present invention makes a faster production possible. The length of the process can be decreased by the simultaneous separation of several circuit chips from the pseudo wafer arrangement. By means of a method according to the invention several groups, e.g. 10×10 circuit chips or series of circuit chips, can be removed from an auxiliary carrier simultaneously and applied with a greater distance between them onto a substrate.
According to the present invention several pick heads which comprise a cross sectional area which is smaller than or as big as the area of the circuit chips to be handled are used. The plurality of pick heads are controlled electronically to position the pick heads on a group of circuit chips. Then the circuit chips are separated from the auxiliary substrate. The individual pick heads can be controlled via a handling device in such a way that, after having picked up the circuit chips, they can be moved apart from each other in a fan shaped form. Then the individual circuit chips can be placed, that is bonded or adhered, in a parallel way, that is simultaneously, or sequentially on the respective carriers, that is the circuit substrate that comprises the electric contacts necessary for contacting the circuit chips, for the final destination.
REFERENCES:
patent: 5447886 (1995-09-01), Rai
patent: 5579441 (1996-11-01), Bezek et al.
patent: 5671530 (1997-09-01), Combs et al.
patent: 5765277 (1998-06-01), Jin et al.
patent: 5809292 (1998-09-01), Wilkinson et al.
patent: 5822608 (1998-10-01), Dieffenderfer et al.
patent: 5840594 (1998-11-01), Tsubouchi et al.
patent: 6338980 (2002-01-01), Satoh
patent: 6451626 (2002-09-01), Lin
patent: 6458623 (2002-09-01), Lin
patent: 0 082 559 (1983-06-01), None
patent: 0 431 637 (1991-06-01), None
patent: 0 660 656 (1995-06-01), None
patent: 0 660 657 (1995-06-01), None
patent: 10 107490 (1998-04-01), None
Patent Abstracts of Japan, vol. 1998, No. 6, Apr. 30, 1998 (JP 10 041695 A).
Haberger Karl
Landesberger Christof
Plettner Andreas
Beyer Weaver & Thomas LLP
Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung
Smith Matthew
Yevsikov V.
LandOfFree
Method for handling a plurality of circuit chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for handling a plurality of circuit chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for handling a plurality of circuit chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3165044