Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2003-01-31
2004-09-07
Zarneke, David A. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S763010
Reexamination Certificate
active
06788095
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor testing, and, more particularly, to a method for wafer sort testing.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) are tested and characterized at different points during the process by which they are fabricated and assembled. The test and characterization data can be used to grade the performance of the ICs, and to eliminate ICs that fail to meet performance standards set by a manufacturer.
One set of tests is performed at “wafer sort.” At this point, the ICs are fully formed, but have not yet been “diced” or separated into individual chips. ICs are typically produced on silicon wafers, each wafer having many ICs. During the wafer sort, a probe card is used to provide test signals to the IC and receive test results from the IC. The probe card touches down on certain input/output (I/O) bonding pads and sends and receives signals through those contact points. The test results are analyzed, and the ICs that fail to meet the required performance standards are discarded when the wafer is diced.
After the ICs are cut from the wafer and separated from each other, and after the ICs that failed the wafer sort test have been eliminated, the remaining ICs are assembled into their packages. The assembly process can involve attaching bond wires or solder bumps to the I/O bonding pads of the IC, connecting the IC to a substrate, and enclosing the IC in a protective package. Once assembly is complete, another set of tests, commonly referred to as “final test,” is performed. At final test, automated test equipment (ATE) tests the performance of the fully assembled ICs, and, as with the wafer sort test, ICs that fail to meet the performance standards set by a manufacturer are discarded.
One common parameter that is tested prior to shipping an IC to a customer is the input leakage current. Input leakage current refers to the static current drawn at an input. Normally, this measurement is made using a precision measurement unit (PMU). If any I/O on an IC shows input leakage current in excess of the maximum set by the manufacturer, the IC is discarded. For example, the Virtex™-II FPGA (field programmable gate array) manufactured by Xilinx®, Inc. of San Jose, Calif. has a maximum absolute value input leakage current of 10 &mgr;A, as specified on its data sheet, “Virtex™-II Platform FPGAs: DC and Switching Characteristics,” Dec. 6, 2002, page 2, DS
031-3
(v2.4). Input leakage can be measured by connecting a PMU to an I/O pad of an IC, either at wafer sort or at final test. In order for the PMU to make the current measurement, the PMU must have access to each I/O pad to be tested.
In some applications, the probe card used at wafer sort does not have access to every I/O pad of an IC. For example, the tests to be performed at wafer sort may only require access to a subset of the I/O pads. As another example, not all of the final, packaged ICs will make use of every I/O pad on the IC, so it can be more cost effective to touch down only on the I/O pads used by every package configuration. In another example, a manufacturer can choose to run wafer sort tests only through certain I/O pads, since testing costs (such as the costs in aligning and maintaining probe cards) increase as the number of accessed I/O pads increases. However, if only certain I/O pads are accessed, the I/O pads that are not accessed by the tester cannot be tested by a PMU, and the leakage current for those I/O pads cannot be determined.
In cases where not every I/O pad is tested at wafer sort, a manufacturer would perform the input leakage test at final test. At final test, all of the I/O pads that are used by an IC in a particular package configuration are connected to package pins, and a manufacturer will typically test all such connected package pins to ensure complete functionality. Testing input leakage at final test, however, increases the cost to the manufacturer, since the manufacturer incurs the assembly costs for ICs that fail to meet the input leakage specification at final test and are rejected and discarded. Had the IC been tested and rejected at the wafer sort test, the manufacturer could have saved at least the cost of assembly.
Therefore, a need exists for a cost-effective method for performing an input leakage test, wherein such test can be performed early in the fabrication process, such as at wafer sort, and without having direct access to the I/O pads to be tested.
SUMMARY OF THE INVENTION
An IC in accordance with the present invention has a resistive element coupled between a voltage reference node, usually power or ground, and an I/O pad. The resistive element is used to inject current to the I/O pad and a detector is used to sense the voltage level of the I/O pad. The test result can be retrieved through an interface such as JTAG. In one embodiment, the resistive element is a transistor that can be selectively enabled by a memory bit.
A method in accordance with the present invention comprises enabling a resistive element coupled between an I/O pad and a voltage reference node, such as power or ground, measuring or detecting a resulting voltage level at the I/O pad, and, based on that result, determining if the input leakage current for that I/O pad exceeds a preset threshold. If so, the IC can be rejected and discarded at the wafer sort test.
REFERENCES:
patent: 5198707 (1993-03-01), Nicolai
patent: 6262585 (2001-07-01), Frodsham et al.
patent: 6313656 (2001-11-01), Schaffroth et al.
patent: 6348810 (2002-02-01), Yanagawa et al.
Xilinx, Inc., “Virtex™-II Platform FPGAs: DC and Switching Characteristics,” Advanced Product Specification, Dec. 6, 2002, p. 2, DS031-3 (v2.4), available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA., 95124.
Mark David
Simmons Randy J.
Liu Justin
Nguyen Jimmy
Xilinx , Inc.
Zarneke David A.
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