Abrading – Abrading process – Combined abrading
Reexamination Certificate
2001-08-07
2004-01-06
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Combined abrading
C451S006000, C451S007000, C451S008000, C451S011000, C451S065000, C451S066000, 43, C438S014000, C438S015000, C438S016000, C438S108000, C438S113000
Reexamination Certificate
active
06672947
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuits (ICs) having flip-chip packaging, and more particularly, to thinning the semiconductor die on which such an integrated circuit is disposed.
BACKGROUND
Demand for flip chip interconnect technology is increasing, because it offers several advantages relative to traditional wire-bond packaging, including better speed performance, higher pin count, smaller form factor, and better heat management. In wire-bond packaging, the electrical interconnection between the crystalline semiconductor die (synonymously, chip) and the carrier (synonymously, package substrate) is made using conductive wires. As illustrated cross section in
FIG. 1
, the die
4
is attached to the carrier
6
with the die
4
front-side face up. An exemplary wire
2
is bonded first to the die
4
, then looped and bonded to the carrier
6
. Wires
2
are typically 1-5 mm in length, and 25-35 microns in diameter. Dies packaged in this manner may be accessed through the front side
7
of die
4
for performing testing and yield analyses. Solder bumps
5
on the underside of the carrier
6
are for external electrical contacts. Mold cap
12
is the top lid of the package.
In contrast, the interconnection between the die
4
and carrier
6
in flip chip packaging is made through conductive “bumps” (e.g., of solder)
8
that are placed directly on the die surface, as illustrated cross section in FIG.
2
. The bumped die is then “flipped over” and placed face down, with the bumps
8
electrically connecting to the carrier
6
directly. The bumps are typically 100-125 microns in diameter.
If the electrical operation of the integrated circuit is to be preserved in its original package, then the only accessible part of the flip-chip packaging for chip repair and/or failure analysis is the “back side”
10
of the die
4
, which typically is a relatively thick silicon substrate. The thickness of the silicon substrate of die
4
is typically about 400 to 800 microns.
The increasing use of such flip-chip packaging for integrated circuits, in turn, has driven the development of failure analysis tools that can be applied to the back side
10
of the die. See, e.g., Campbell, Ann N. et al., “Die Backside FIB Preparation for Identification and Characterization of Metal Voids,” Proceedings from the 25
th
International Symposium for Testing and Failure Analysis, pp.317-325, 1999.
In order to access the internal nodes of an integrated circuit device to perform failure diagnostics and/or yield analyses using optical techniques or a charged-particle beam, the thickness of die
4
must be reduced to a workable (penetrable) range, usually 100 microns or less. More sophisticated techniques require an even thinner silicon substrate.
To perform such back side failure analysis or circuit editing using focused ion beam (FIB), a three-step process is currently used. In the first step, a flip-chip packaged die as shown in
FIG. 3A
in a perspective view is typically mechanically globally thinned (i.e., thinned over its entire surface area) such that the remaining silicon thickness, t, is around 100 microns, as illustrated in FIG.
3
A. The pre-thinning thickness is shown by the broken lines. Using existing lapping techniques for this stock removal step, yield drops when the die is thinned to less than 100 microns. (That is, there is excessive breakage of the die
4
). As will be understood by those of ordinary skill in the art,
FIG. 3A
actually depicts a packaged die as in
FIG. 2
with solder bumps
5
on its underside serving as the contacts; the back (top) side of the die
4
has been exposed by removing the top of the package. The other detail of
FIG. 2
is omitted for simplicity.
After this silicon removal, alignment points
9
(typically three or more) are exposed and identified on the corners of die
4
to assist in navigation of a tool about the die
4
, as illustrated in FIG.
3
B. This process is referred as “Global alignment”. For example, a FIB system commercially available as the “IDS P3X” (Precision Probe Point extension) system, from Schlumberger Technologies, Inc., San Jose, Calif., provides software-based navigation tools in which the CAD layout and live FIB images of the die can be registered to one another. Once registered, these images are linked so that when the user selects a point or feature on one of the images, the corresponding location is identified on the other image. Note that fiducial marks are built into the circuit layer and are not on the surface. Therefore there is a need to expose the marks by removing the silicon above the marks before the alignment processes.
In the second step (FIG.
3
C), one or more local “trenches”
13
are defined in the silicon substrate of die
4
, with a trench area size between about 100 and 400 microns
2
. Currently, either laser micro-chemical etching (LMC) or the focused ion beam (FIB) is used to define the trench. While the laser micro-chemical etching method for trenching is fast and reliable, it is also very expensive. Typical systems, which include the laser and sophisticated, but necessary, navigation software, cost around $1.5M. An FIB system, while less expensive ($500K-$1M), is also much slower. Etching a 100 microns
2
trench in a die with an FIB device typically takes about 30 minutes.
The distance d from the bottom of the trench
13
to the underlying active circuit layers is only 10 microns at most, as illustrated in
FIG. 3D
in partial cross section.
FIGS. 3D
,
3
E show only a small part of the die; other illustrated structures are the passivation
19
and metal layers
15
a
,
15
b
. Also provided is silicon dioxide deposition layer
21
. Moreover, trenching using either LMC or FIB techniques requires an additional thickness measuring tool integrated into the system to monitor the trenching progress. Optical beam induced current (OBIC) and imaging techniques are being used for this purpose. However, either an additional laser system or a high end imaging system is needed to measure silicon thickness inside the trench, further complicating overall requirements for the system.
In the third step (FIG.
3
E), an FIB (focussed ion beam) system is used to mill to the circuit layer
17
with small openings
23
a
,
23
b
to perform a circuit edit through the bottom of the trench
13
formed in the second step. A circuit edit can include shorting circuit elements, cutting a trace (metal layer interconnect), and changing an interconnect
15
a
,
15
b
. The FIB system is typically used in conjunction with an etchant gas (for example, XeF
2
) for milling and quick, uniform removal of the silicon substrate. However, there is an aspect ratio (hole depth vs. hole opening) limitation in the use of an FIB device. Practically, the FIB hole
23
a
,
23
b
aspect ratio is less than 10:1 for the backside circuit edit. Therefore, the trench is preferably made as deep as possible within the silicon substrate. For the circuit edit, metal deposition
25
is provided while metal layer
15
a
is cut.
In accordance with this method, the accuracy of ion beam placement inside the trench to perform a circuit edit is very dependent on stage movement accuracy, after the global registration of the die to the CAD layout. This is due to the fact that the ion beam of the FIB device cannot image through silicon, and optical imaging techniques cannot provide useful data for guiding the ion beam, due to surface roughness inside the trench after LMC is performed or the FIB device is used. In addition, as device (transistor) size shrinks and the die size increases in modem ICs, device navigation and achieving accurate ion beam placement will become more difficult.
Thus, existing processes for preparing a die having flip chip packaging for an FIB circuit edit is time-consuming (especially when trenching is required at several locations in the same die), expensive (because a sophisticated tool is required to make the trenches), and non-ideal for optical imaging (because a trench is too rough to image optically).
The recently develop
Tsao Chun-Cheng
Valliant John
Hail III Joseph J.
McDonald Shantese
NPTest LLC
Wenocur Deborah
LandOfFree
Method for global die thinning and polishing of flip-chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for global die thinning and polishing of flip-chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for global die thinning and polishing of flip-chip... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3217231