Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
2011-02-22
2011-02-22
Yenke, Brian (Department: 2422)
Television
Synchronization
Automatic phase or frequency control
C348S441000, C348S537000, C348S525000, C348S581000, C348S790000, C348S797000, C345S698000
Reexamination Certificate
active
07893997
ABSTRACT:
A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The target image frame corresponds to a source image frame. The frame pixel number is the number of total pixels included in a predetermined frame format, and the Vsync signal is an input Vsync signal or an output Vsync signal. The period of the output clock signal is the result of the period of the Vsync divided by the frame pixel number. In this manner, the format of the target image frame can remain substantially fixed, and is substantially equal to the predetermined frame format.
REFERENCES:
patent: 5739867 (1998-04-01), Eglit
patent: 5790096 (1998-08-01), Hill, Jr.
patent: 5914757 (1999-06-01), Dean et al.
patent: 5933196 (1999-08-01), Hatano et al.
patent: 6130721 (2000-10-01), Yoo et al.
patent: 6480235 (2002-11-01), Sugawa et al.
patent: 6522365 (2003-02-01), Levantovsky et al.
patent: 6532042 (2003-03-01), Kim
patent: 6636269 (2003-10-01), Baldwin
patent: 6654065 (2003-11-01), Sung
patent: 6721016 (2004-04-01), Hamajima
patent: 6853354 (2005-02-01), Asamura
patent: 6891572 (2005-05-01), Ueki
patent: 7061540 (2006-06-01), Weaver et al.
patent: 7071992 (2006-07-01), Chen et al.
patent: 7158186 (2007-01-01), Selby et al.
patent: 7193657 (2007-03-01), Chida
patent: 7239355 (2007-07-01), Smith et al.
patent: 7289170 (2007-10-01), Jun
patent: 7307643 (2007-12-01), Moroo et al.
patent: 7327400 (2008-02-01), Greenberg
patent: 7333149 (2008-02-01), Choi
patent: 7345709 (2008-03-01), Chang et al.
patent: 7359007 (2008-04-01), Wu
patent: 2002/0005840 (2002-01-01), Wicker
patent: 2005/0012738 (2005-01-01), Gong et al.
patent: 2005/0078126 (2005-04-01), Park et al.
patent: 2006/0152624 (2006-07-01), Cho et al.
REALTEK Semiconductor Corp.
Thomas Kayden Horstemeyer & Risley LLP
Yenke Brian
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