Method for generating verification tests

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324 73R, 371 15, G01R 3128

Patent

active

046929215

ABSTRACT:
A method for developing test sequences that verify the operation of a finite state machine. The method includes developing a set of unique input/output sequences for the various states of the machine and constructing a test sequence for each edge of the machine. The test sequence is a concatenation of a head sequence that brings the machine to the head state of the tested edge, the input/output sequence associated with the tested edge, and a unique input/output sequence which verifies that the machine entered the expected tail state.

REFERENCES:
patent: 4519078 (1985-05-01), Komonytsky
patent: 4601032 (1986-07-01), Robinson
patent: 4604744 (1986-08-01), Littlebury

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