Method for generating transistor placement in an automatic cell

Details Method for generating transistor placement in an automatic cell Method for generating transistor placement in an automatic cell

1997-03-07

1999-11-30

Teska, Kevin J.

39550003, 39550008, 39550009, 39550012, G06F 1750

Patent

active

059957344

ABSTRACT:
As a method for determining transistor palcement of a cell by using a computer, a degree of integratin of the cell equivalent to manual layout design can be realized and a processing can be performed within a practical time. At a one-dimensional placement step, transistors of the cell are placed in a string with vertical placement state in each channel region. At a two-dimensional placement step, conditions of the one-dimensional placement step are excluded, and the transistors can be placed in a plurality of strings with horizontal placement state in each channel region to strings with horizontal placement state in each channel region to change the transistor placement. Consequently, a result of the transistor placement obtained at the one-dimensional placement step can be improved and the cell can be made more compact. At the one-dimensional placement step, global optimization is performed. At the two-dimensional step, only local improvement of the placement is performed. Therefore, a burden on the computer can be relieved more considerably than in a method for placing transistors in two-dimensions from the beginning, and the processing can be performed within the practical time.

REFERENCES:
patent: 5633807 (1997-05-01), Fishburn et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5675501 (1997-10-01), Aoki
patent: 5701255 (1997-12-01), Fukui
patent: 5737236 (1998-04-01), Maziasz et al.
Saika et al "A Two-Dimensional Transistor Placement for Cell Synthesis," IEEE, pp. 557-562, Mar. 1997.
Tani et al. "Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits," IEEE, pp. 490-493, 1991.
Srinivas Davadas "Optical Layout Via Boolean Satisfiability," IEEE, pp. 294-297, 1989.
Levebvre et al "Transistor Placement and Interconnect Algorithms for Leaf Cell Synthesis," IEEE, pp. 119-123, 1990.
Hsieh et al "LIB: A CMOS Cell Compiler," IEEE, pp. 994-1005, Aug. 91.
Chen et al "The Layout Synthesizer an Automatic Netlist-To-Layout System," ACM/IEEE, pp. 232-238, 1989.
Takao Uehara et al., "Optimal Layout of CMOS Functional Arrays" IEEE Transactions on Computers, vol. C-30, No. 5, pp. 305-312, May, 1981.
Donald G. Baltus et al., "SOLO: A Generator of Efficient Layouts From Optimized MOS Circuit Schematics", 25th ACM/IEEE Design Automation Coference, pp. 445-452, 1988.
Charles J. Poirier, "Excellerator: Custom CMOS Leaf Cell Layout Generator", IEEE Transactions on Computer-Aided Design, vol. 8, No. 7, pp. 744-755 Jul., 1989.
Chi Yi Hwang et al., "An Efficient Layout Style for Two-Metal CMOS Leaf Cells and Its Automatic Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 3, pp 410-424, Mar. 1993.

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