Method for generating test sequences for detecting faults in tar

Details Method for generating test sequences for detecting faults in tar Method for generating test sequences for detecting faults in tar

1995-10-17

1997-04-01

Nguyen, Hoa T.

Excavating

371 27, G06F 1100

Patent

active

056174276

ABSTRACT:
This invention is intended for a semiconductor integrated circuit with scan logical blocks wherein scan flip-flops are used for interblock signal communication. A testing sequence is generated to detect a fault in a target scan logical block. First, a block testing sequence, which is a testing sequence to the scan logical block as a single circuit, is generated. If signal inversion occurs in a scan chain that runs through the scan logical block, data that is inputted to or outputted from the scan logical block via such a scan chain is inverted. Patterns equal in number to the semiconductor integrated circuit's structure are placed in front of and behind a shift-in pattern and a shift-out pattern in the block testing sequence, to convert the block testing sequence into a testing sequence for the entire semiconductor integrated circuit. Upon completion of all the testing sequence generation with respect to the scan logical blocks, the generated testing sequences are merged.

REFERENCES:
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
patent: 5500861 (1996-03-01), Oppedahl
patent: 5504756 (1996-04-01), Kim et al.

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