Method for generating test patterns to detect an electric shortc

Details Method for generating test patterns to detect an electric shortc Method for generating test patterns to detect an electric shortc

1992-11-18

1997-06-03

Voeltz, Emanuel T.

Excavating

G06F 1100

Patent

active

056362293

ABSTRACT:
A method for generating test patterns to detect an electric shortcircuit, a method for testing electric circuitry while using test patterns so generated, and a tester device for testing electric circuitry with such test patterns. If electric circuitry comprises a plurality of separate nets, a short circuit between an arbitrary pair of nets may be detected by driving the first net at logic zero and the second net at logic one. Measuring the two effective net potentials of the pair of nets will then reveal the short in that two equal potentials would occur. In the case of CMOS technology the driving patterns should also comprise the inverse of the combination above, and also for each pair of nets the number of non-identical overall patterns having the particular 1/0 and 0/1 combinations should be guaranteed and adjustable. The total number of patterns should be minimal. In a test pattern matrix, each column is a single overall pattern; each row is the sequence of signals for the net in question. Each pair of nets is then differentially driven at least twice, either in one, or in both polarities. The minimum Hamming distance between the various rows is equal to two. For the number of nets equal to N the minimum number of test patterns P obeys

REFERENCES:
patent: 5027353 (1991-06-01), Jarwala et al.
patent: 5430735 (1995-07-01), Sauerwald et al.
Wakerly, Digital Design Principles and Practices, Chpt. 1, pp. 33-36 1990.
McBean et al., "Bridging Fault Algorithms for a Boundary Scan Board," IEE Colloq, 1990, No. 183: Application and Development of the Boundary Scan pp. 1-8.
IEEE Standard 1149.1-1190 "Standard Test Access Port and Boundary Scan Architecture" 1990.

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