Image analysis – Applications – Reading maps – graphs – drawings – or schematics
Reexamination Certificate
1998-12-03
2001-12-18
Boudreau, Leo (Department: 2621)
Image analysis
Applications
Reading maps, graphs, drawings, or schematics
C382S176000, C702S119000, C703S014000, C707S793000
Reexamination Certificate
active
06332032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fields of electronic circuit design and testing. In particular, the present invention relates to the automatic conversion of test pattern drawings of electrical circuits into test files which can be used as direct input to computer-aided design (CAD) tools or integrated circuit (IC) testing equipment.
2. Background of the Invention
Currently, the Department of Defense (DoD) maintains a large inventory of documentation for electronic systems. The existing documentation is in the form of circuit drawings, test pattern drawings, and associated information. Many of these documents have already been scanned and are stored as scanned image files. However, these files are only abstract representations of circuits, and as such cannot be directly used as input to computer-aided design (CAD) tools or integrated circuit (IC) testers. In order to re-specify or re-manufacture an electronic part, board, or system, a considerable amount of time and human effort must be expended to collect and understand the circuit information, such as inputs and outputs, from the circuit drawing. In order to ensure that the re-designed device is functioning correctly, the test pattern drawings, which specify the response to stimulus expected of electronic circuits, must also be converted into a form that can be used for simulation and IC testing.
The ability to re-specify and re-manufacture circuits is essential for DoD and industry to efficiently and automatically maintain and upgrade system electronics. This ability particularly affects those organizations concerned with building and maintaining fleets of high-cost, long-lived electronic-dependent systems facing the same problems associated with maintaining proper documentation, continuous upgrades, the obsolescence of commercial integrated circuit (IC) technology, and document storage and retrieval.
The term “test pattern drawing” is defined as a document, such as a test word truth table, specifying testing characteristics of a given circuit or component, rather than a drawing in the pictorial sense. For example, a typical test pattern drawing is composed of multiple pages where each page contains test pattern information and data arranged in a tabular format of rows and columns. This format is defined as the “test word truth table” drawing, and it is important to recognize that no schematic or drawing in the conventional pictorial sense is provided. These definitions apply in conjunction with any other commonly accepted definitions of these terms.
A test pattern drawing describes a properly functioning IC by listing the input patterns, or test words, supplied to the IC being tested and the corresponding output patterns. Other relevant information, including the pin names and/or pin numbers, test line numbers, and whether or not the output is to be tested is also typically included in the drawing. The information contained in a test pattern drawing is only intelligible to a trained human observer who first interprets the information content of the drawing based on specialized knowledge and experience and then manually enters the test pattern information as needed in CAD tools or IC testers.
A complete set of test patterns, even for a simple device, will generally consist of a number of drawing pages. The drawing set for test patterns alone can become especially large for complicated devices which typically require over 250,000 test vectors. Therefore, the productivity improvement in automating this manual process for circuit and board re-design and re-engineering is particularly significant.
Until now there has been no cost-effective, automatic way to convert the test information from the “test word truth table” of a test pattern drawing into a machine-readable data file format. There has been no method that accurately reproduces the necessary input and output information in CAD format to readily replicate the equipment's test parameters without human intervention.
Therefore, there is a long-felt need in the art to automatically convert test pattern data from a “test word truth table” into a machine-readable format, such as a specially formatted text file. Such a file can be used by a CAD tool to provide input stimulus to a simulation model to check the model's responses and verify that the model is providing the correct outputs. Similarly, such a machine-readable file can be used by IC testing equipment to generate input stimuli to the IC's input pins and to check the output observed at the IC's output pins to verify that the physical device is functioning properly. The present invention addresses this need for efficient and cost-effective methods suitable for use with CAD technology.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide a method for directly and automatically importing the information contained in the test word truth table of a test pattern drawing into a computer-aided design (CAD) tool. This information can then provide stimuli to a CAD model without human intervention for the understanding of the drawing and without an operator using the CAD tool design entry features to manually enter the test pattern information into the required input format of the CAD tool.
Another object of the present invention is to provide a method for directly and automatically importing the information contained in a test pattern drawing into integrated circuit (IC) testing equipment. This information can then provide stimuli to an IC being tested without having to manually enter the test pattern information into the required input format of the IC tester.
These and other objects are accomplished by the following steps to convert a test word truth table of a test pattern drawing into a machine readable file format for use by electronic computer aided design software tools and by integrated circuit test equipment. These steps include scanning the test word truth table of a test pattern drawing; producing a graphical bitmap image of the scanned test pattern drawing; locating and removing non-essential test pattern data; recognizing the essential test pattern information from the bitmap image; storing the desired data in tabular format; integrating the stored test path data into a machine-readable format; and converting the recognized test pattern data into a machine-readable test file.
The present invention therefore provides a method for effectively converting the test word truth table in test pattern drawings, which contain essential information for parts re-design and re-procurement, into a usable format for CAD tools and IC testers. The advantages of the present invention can be further appreciated in view of a related application, Ser. No. 08/506,943, “Method for Generating Computer Aided Design Programming Circuit Designs from Scanned Images of the Design”, filed Jul. 26, 1995, which is hereby incorporated by reference. In the referenced application, a method is described for transforming scanned pictorial schematic circuit drawings into a machine-readable non-pictorial description readily usable CAD input.
The present invention also includes a computer program stored in computer-readable memory, and implemented by a general-purpose computer.
REFERENCES:
patent: 4541114 (1985-09-01), Rutenbar et al.
patent: 4559644 (1985-12-01), Kataoka et al.
patent: 4791586 (1988-12-01), Maeda et al.
patent: 4949388 (1990-08-01), Bhaskaran
patent: 4984279 (1991-01-01), Kidney et al.
patent: 5222158 (1993-06-01), Takasaki et al.
patent: 5251268 (1993-10-01), Colley et al.
patent: 5325441 (1994-06-01), Hoecker
patent: 5467411 (1995-11-01), Tanaka et al.
patent: 5568397 (1996-10-01), Yamashita et al.
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5832415 (1998-11-01), Wilkening et al.
patent: 5918192 (1999-07-01), Tomaszewski
patent: 6134338 (2000-10-01), Solberg et al.
Shinya Inoue, Video Microscopy, Plenum Press, ISBN 0-306-42120-8, pp. 26.*
Medhat Kirma et al., From Paper Drawings to Computer-Aided Design, IEEE Computer G
Dukes Michael A.
Michael Gerald T.
Su Wei
Boudreau Leo
O'Meara John M.
The United States of America as represented by the Secretary of
Werner Brian P.
Zelenka Michael
LandOfFree
Method for generating test files from scanned test vector... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for generating test files from scanned test vector..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for generating test files from scanned test vector... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2556370