Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Pulse repetition rate
Reexamination Certificate
2008-07-01
2008-07-01
Do, Chat C. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Pulse repetition rate
C708S270000
Reexamination Certificate
active
07395286
ABSTRACT:
A divide-by-N clock frequency divider producing N non-overlapping clocks each with precise 1/N duty ratio is implemented by a counter, a token generator and N-bit shift register. Every N clock cycles, a pulse is generated as a token from a logical combination of signals from the counter. The pulse is passed along a shift register having balanced load capacitances under control of the clock edge, ensuring a precise 1/N duty ratio that is unaffected by load capacitances from the fault state detection and/or reset circuitry. In this manner, a higher operating frequency may be achieved with low power consumption.
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Koh Yongseon
Mohan Jitendra
Do Chat C.
National Semiconductor Corporation
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