Method for generating logic circuit data

Details Method for generating logic circuit data Method for generating logic circuit data

1987-09-23

1988-07-19

Harkcom, Gary V.

Boots, shoes, and leggings

364490, G06F 1560

Patent

active

047589531

ABSTRACT:
In automatic development of the higher hierarchic logic into the lower hierarchic logic in a hierarchic logic designing, identification codes are beforehand assigned to logic components of the higher hierarchic logic, and the identification codes are also assigned to the lower hierarchic logic data when developing the higher hierarchic logic into the lower hierarchic logic in order to establish correspondences between the higher and lower hierarchic logic, thereby allowing a higher-speed logic compare operation with respect to a design change on the higher or lower hierarchic logic and enabling the automatic update of the lower hierarchic logic by use of the higher hierarchic logic as the master.

REFERENCES:
patent: 4020466 (1977-04-01), Cordi
patent: 4084231 (1978-04-01), Capozzi
patent: 4263651 (1981-04-01), Donath et al.
patent: 4464712 (1984-08-01), Fletcher
patent: 4584653 (1986-04-01), Chih et al.
patent: 4600995 (1986-07-01), Kinoshita
patent: 4602339 (1986-07-01), Aihara
patent: 4607339 (1986-08-01), Davis
patent: 4612618 (1986-09-01), Pryor
patent: 4613940 (1986-09-01), Shenton et al.

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