Method for generating efficient testsets for a class of digital

Details Method for generating efficient testsets for a class of digital Method for generating efficient testsets for a class of digital

1987-08-31

1989-08-29

Lall, Parshotam S.

Boots, shoes, and leggings

324 73AT, 371 24, 371 27, 371 23, G01R 3128

Patent

active

048623997

ABSTRACT:
A digital logic circuit is broken into functional blocks, each having a path from its output port to a chip level output port. No two input patterns to that path produce the same output pattern on that path and for every path input pattern there is a one-to-one relation with the path output pattern regardless of the transformation of that pattern by the path. All other path inputs are independent of the path test patterns such that a block test output pattern applied to that path is not fault affected by those other path inputs. The circuit is partitioned into testable blocks whose outputs are coupled by such paths to observable chip output ports. The chip level tests for all block test patterns are screened to eliminate redundant block tests to produce a practical set of test vectors.

REFERENCES:
patent: 4656592 (1987-08-01), Spaanenburg et al.
patent: 4692920 (1987-09-01), Tannhaeuser et al.
patent: 4692921 (1987-09-01), Dahbura et al.
patent: 4696006 (1987-09-01), Kawai
patent: 4701922 (1987-10-01), Kuboki et al.
patent: 4725975 (1988-02-01), Sasaki
patent: 4745355 (1988-05-01), Eilhelberger et al.
Edward J. McCluskey, "Design for Autonomous Test," IEEE Transactions on Computers, vol. C-30, No. 11, Nov., 1981, pp. 866-874.
Magdy S. Abadir et al., "A Knowledge-Based System for Designing Testable VLSI Chips," IEEE Design & Test, Aug. 1985, pp. 56-58.
Magdy S. Abadir et al., "Test Schedules for VLSI Circuits Having Built-In Test Hardware," IEEE Transactions On Computers, vol. C-35, No. 4, Apr. 1986, pp. 361-367.
Smith Freeman, "The F-Path Method of Test Generation for Datapath Logic," Proceedings of Custom Integrated Circuit Conference, Portland, Oregon, May 4-7, 1987.

Affiliated with

Also associated with

Rating

Method for generating efficient testsets for a class of digital does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for generating efficient testsets for a class of digital , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for generating efficient testsets for a class of digital will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2245137