Image analysis – Applications – Reading maps – graphs – drawings – or schematics
Reexamination Certificate
1995-07-26
2001-11-06
Patel, Jayanti K. (Department: 2623)
Image analysis
Applications
Reading maps, graphs, drawings, or schematics
C250S559340, C382S145000, C700S121000
Reexamination Certificate
active
06314194
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fields of electronic circuit design languages and pattern recognition software applications and more particularly, to the conversion of scanned images of schematic diagrams of electrical circuits into computer aided design programs/tools and/or VHSIC Hardware Description Language (VHDL) or similar electronic circuit description languages.
BACKGROUND OF THE INVENTION
Currently, the Department of Defense maintains a large inventory of documentation for electronic systems. Usually, this existing documentation is in the form of schematic drawings of electronic circuitry either in hard copy (paper or other similar media) or in a scanned image file. The term schematic drawing shall refer to a drawing that shows by means of graphic symbols, the electrical connections and functions of a specific circuit arrangement. In order to respecify or remanufacture these electronic circuits, as a part, board or system, a considerable amount of time and human effort is required to collect and understand the circuit information from the circuit drawing. Most of this time today is spent recreating the schematic drawing into a computer-aided design (CAD) software program or into a circuit description language. The ability to respecify and remanufacture electronic circuits is essential to the Department of Defense's and industry's ability to maintain and upgrade system electronics.
CAD programs put the information from the drawing into netlist formats. A netlist is a representation of a circuit in a form which lists a series of nets and shows the ports of which circuit are connected to each net. A net is a single electrical path in a circuit having the same signal value at all points wherein a single net can connect to multiple components. CAD programs use either a standard or a proprietary format to store netlist information about a circuit in a form that is generally easy to transfer to other CAD programs and is linked to situational models, which allow direct links between the design, modeling, simulation, and manufacturing phases of the circuit design.
In addition to the proprietary formats (generally used with a single software developer's CAD program), there are a number of standard formats for information exchange within and between different CAD developers. Though the details of these formats may differ, the basic information is the same: components and interconnections between the components. The VHDL is an industry and Department of Defense standard for the documentation, design and simulation of digital electronic circuitry. VHDL is a human and computer readable format used to import design information directly into CAD programs. (The other different types of circuit description languages exist, such as Verilog Hardware Description Language and the Electronic Design Interchange Format (EDIF), are similar to VHDL in concept, and are used for design transfer, but differ in other details which are not pertinent to this disclosure.) Most commercial CAD programs provide a fully automated and integrated manufacturing path from VHDL documentation to integrated circuit fabrication. Since VHDL provides manufacturing technology independent documentation of a digital integrated circuit, it is ideal for the purpose of documenting Department of Defense and industry digital electronic systems for system upgrades and full life cycle support.
Although scanned images of schematic drawings have been generally used in computerized document management systems, these scanned images have not been effectively used in CAD or electronic circuit description languages because these images lack the necessary format information concerning the components and interconnections that are required by these programs/languages. Although research has been conducted in recognizing scanned electronic circuit drawings, these efforts have primarily focused on symbol recognition and character extraction. See for example “Circuit Comparison by Hierarchical Pattern Matching,” by Pelz et al,
Proceedings of
1991
Conference on Computer
-
Aided Design,
November 1991, Pp 290-293; “A New Input Method for CAD-Automatic Read In Technique Of Paper Drawings,” by Shi et al,
Proceedings of
1991
International Conference on Circuits and Systems,
June 1991, pp 431-433; “Representation, Classification and Modelling of Graphs for Efficient Pattern Recognition in Line Images,” by Maderlecher et al,
Proceedings of the
9
th
International Conference on Pattern Recognition,
November 1988, vol. 2, pp. 678-680; and “A Knowledge-Based Graphic Description Tool for Understanding Engineering Drawings,” by Yu et al,
Proceedings of the
1
st
International Conference on Systems Integration,
April 1990, pp. 302-309. However, to date, there has been no publications or references to devices that extract circuit interconnections based on a full schematic understanding or a generation of a complete netlist representation from a scanned image. Accordingly, there is a need in this art to provide a complete bridge between scanned images of schematic drawings and the functional CAD or description language formats of the schematic drawings.
The present invention addresses such a need.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a method of converting scanned images of schematic drawings into a functional netlist which can be used in either a CAD program or in a description language of an electronic circuit such as VHDL.
It is another objective of this invention to provide a means to not only recognize elements and sub elements of electronic circuit, but also to recognize the connectivity and signal flow between the circuit elements and subelements.
These and other objectives are accomplished by the following generic steps:
a. producing a bitmap image of a schematic using standard scanning devices that takes a paper drawing and produces an image of a drawing in electronic form where the white and black parts of the drawing image are represented by different values, for example,
0
representing white and
1
representing black;
b. locating and identifying the text portions of the schematic which is used later to tag signal and pin names to reassemble hierarchical schematic drawing sets into models where the links between the various schematic drawings are included in the model;
c. locating and identifying the drawing symbols, such as logic gates, transistors, and resistors, as well as the pins that link one schematic drawing to other schematics in a set of drawings;
d. locating and identifying the signals (or nets) wherein the individual signal paths are located and identified, the inversion circles, which are critical to the correct identification of component function, are located and the ports (connections to signals) for each component are located and identified;
e. integrating the information about component type, ports, inversion circles, and fanouts (number of input ports driven by an output port) to uniquely identify each component; and
f. combining the component information with the signal information to provide all of the information required to generate the netlist in the desired form (VHDL, Verilog, EDIF, or other).
Specifically, after the image is in an electronic format, symbol recognition software and algorithms, which are known to those skilled in the art, are used to identify the various components of the schematic. Then, the signal flow of the schematic is recognized by three independent steps: 1) detecting all signal crossovers; 2) exploring contiguous blocks and assigning all signal crossovers an appropriate pseudo-contiguous block identification; and 3) extracting the signal images from the contiguous blocks using the methods of the present invention. The location and identification of the contiguous signal blocks can be accomplished according to the present invention in one or a combination of several ways. One method involves finding the contiguous blocks one after another and then searching over the entire sca
Dukes Michael A.
Michael Gerald T.
Su Wei
Patel Jayanti K.
The United States of America as represented by the Secretary of
Zelenka Michael
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