Method for generating chip stacks

Details Method for generating chip stacks Method for generating chip stacks

2006-08-08

2006-08-08

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

With attachment to temporary support or carrier

C438S118000, C438S114000, C438S977000, C438S460000, C438S455000, C438S458000, C438S459000, C257S686000, C361S790000

Reexamination Certificate

active

07087502

ABSTRACT:
Disclosed is a method for generating chip stacks during the production of chips from wafers, the chips located on the wafer being separated from one another, the wafer being ground thin and the chips being stacked to form chip stacks, the chips being checked for the purpose of a functional check, characterized in that the chips are checked in a first work step, that adhesive material is applied on the good chips, whereas the bad chips are not provided with adhesive material, that the wafer is assembled and ground thin afterwards and that the bad chips are subsequently removed and replaced by good chips.

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patent: 4433845 (1996-03-01), None
patent: 19856573 (2000-05-01), None
patent: WO 01/18851 (2001-03-01), None
patent: WO 01/29881 (2001-04-01), None

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