Method for generating a topology map for a serial bus

Details Method for generating a topology map for a serial bus Method for generating a topology map for a serial bus

1994-09-27

1998-03-03

Bowler, Alyssa H.

Boots, shoes, and leggings

39520068, 39520079, 39520083, 364DIG1, G06F 1300

Patent

active

057245177

ABSTRACT:
A method and system for mapping a node topology is disclosed. The node topology is based on a computer system comprised of a high performance acyclic serial bus and a plurality of nodes coupled to the acyclic serial bus. Each node further includes an identification packet. The mapping topology establishes a root node based upon information found in each identification packet and establishes at least one branch node among the nodes based on the information. Next, the topology mapping method selects a first available branch node among the available branch nodes based on the information. The system then identifies any of the nodes that are child nodes to the first available branch node. Upon identifying all child nodes of the branch node, the system selects a next available branch node based upon the information. The processing continues until the root node is processed as a branch node.

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"IEEE Standard for a High Performance Serial Bus", The Institute Of Electrical And Electronic Engineers, Inc. Draft 7.1v1, IEEEP1394, Aug. 5, 1994.
Marazas, et al., "Information Technology--SCSI-3 Serial Bus Protocol (SBP)", X3T10 992D, Rev. 18, Working Draft, Aug. 11, 1994.

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