Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-06-06
2006-06-06
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S026000, C710S269000, C714S736000, C716S030000
Reexamination Certificate
active
07058557
ABSTRACT:
A method for functional verification of hardware design. First, a first memory region storing a test pattern and a second memory region storing interrupt instructions are provided. Then, the test pattern stored in the first memory is hardware-simulated. If an external interrupt is received during the simulation of the test pattern, the second memory region is accessed and the interrupt instructions are hardware-simulated. Thereafter, the simulated result of the interrupt instructions is self-tested to obtain a first verification result, and the hardware design is verified according to the first verification result.
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Faraday Technology Corp.
Hsu Winston
Phan Thai
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