Method for fully planarized conductive line for a stack gate

Details Method for fully planarized conductive line for a stack gate Method for fully planarized conductive line for a stack gate

1997-12-17

2000-07-25

Niebling, John F.

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438587, 438593, 438631, 438633, 438683, H01L 213205, H01L 214763, H01L 2144, H01L 21302

Patent

active

060936509

ABSTRACT:
A method for substantially reducing conductive line cracking on an integrated circuit, comprising the steps of: obtaining a semiconductor structure with a first surface and with an insulating region adjacent to and rising above the first surface; and forming a layer of a first conductive material above the first surface of the semiconductor structure and above the adjacent first insulating region. Additionally the method includes forming an opening through the layer of first conductive material down to the first insulating region; polishing the layer of first conductive material; and forming an insulation layer over the layer of first conductive material. The method further includes the steps of forming a layer of a second conductive material above the insulation layer; polishing the layer of second conductive material; and forming a third conductive layer above the layer of second conductive material.

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