Method for forming via hole in multiple metal layers of semicond

Details Method for forming via hole in multiple metal layers of semicond Method for forming via hole in multiple metal layers of semicond

1992-10-01

1994-12-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437245, H01L 2144

Patent

active

053729714

ABSTRACT:
A method for forming a via hole in multiple metal layers of the semiconductor device is disclosed. In a via hole forming process of the semiconductor device, a barrier layer is formed beneath the photoresistive layer. Accordingly, the polymer residue formed on the metal-layer pattern and side wall of the via hole is prevented during the plasma etching process.

REFERENCES:
patent: 4997789 (1991-03-01), Keller et al.

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