Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Patent
1997-08-22
2000-06-27
Bowers, Charles
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
438107, 438109, 438110, 438119, 438130, 438612, H01L 2144, H01L 2148, H01L 2150, H01L 2182
Patent
active
06080596&
ABSTRACT:
A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. A dielectric coating is applied to the die to provide a conformal coating to protect and insulate the die and a laser is used to ablate the area over the bond pads to remove the dielectric coating in order to provide for electrical connections to the bond pads.
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Sautter Kenneth M.
Vindasius Alfons
Bowers Charles
Cubic Memory Inc.
Jones Josetta
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