Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Patent
1997-08-22
1999-04-06
Niebling, John F.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
438113, 438119, 438455, H01L 2144, H01L 2148, H01L 2150
Patent
active
058917616
ABSTRACT:
A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. A thermally conductive epoxy preform is provided between the stack of segments so that the stack of segments are epoxied together. In one embodiment, the thermally conductive epoxy preform includes a plurality of glass spheres randomly distributed within the preform to maintain a distance between the stack of segments.
REFERENCES:
patent: 3679941 (1972-07-01), Lacombe et al.
patent: 3691628 (1972-09-01), Kim et al.
patent: 3702025 (1972-11-01), Archer
patent: 3769702 (1973-11-01), Scarbrough
patent: 3813773 (1974-06-01), Parks
patent: 3999105 (1976-12-01), Archey
patent: 4300153 (1981-11-01), Hayakawa
patent: 4426773 (1984-01-01), Hargis
patent: 4525921 (1985-07-01), Carson et al.
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4613891 (1986-09-01), Ng et al.
patent: 4646128 (1987-02-01), Carson et al.
patent: 4659931 (1987-04-01), Schmitz
patent: 4672737 (1987-06-01), Carson et al.
patent: 4677528 (1987-06-01), Miniet
patent: 4703170 (1987-10-01), Schmitz
patent: 4706166 (1987-11-01), Go
patent: 4761681 (1988-08-01), Reid
patent: 4764846 (1988-08-01), Go
patent: 4783695 (1988-11-01), Eichelberger
patent: 4801992 (1989-01-01), Golubie
patent: 4803595 (1989-02-01), Kraus
patent: 4807021 (1989-02-01), Okumura
patent: 4827327 (1989-05-01), Miyauchi et al.
patent: 4862249 (1989-08-01), Carlson
patent: 4894706 (1990-01-01), Sato et al.
patent: 4897708 (1990-01-01), Clements
patent: 4901136 (1990-02-01), Neugebauer et al.
patent: 4907128 (1990-03-01), Solomon
patent: 4939568 (1990-07-01), Kato
patent: 4941033 (1990-07-01), Kishida
patent: 4954875 (1990-09-01), Clements
patent: 4956694 (1990-09-01), Eide
patent: 4956695 (1990-09-01), Robinson
patent: 4956746 (1990-09-01), Gates et al.
patent: 4959749 (1990-09-01), Dzarnoski
patent: 4983533 (1991-01-01), Go
patent: 4989063 (1991-01-01), Kolesar, Jr.
patent: 4996583 (1991-02-01), Hatada
patent: 5006923 (1991-04-01), Warren
patent: 5013687 (1991-05-01), Solomon
patent: 5019943 (1991-05-01), Fassbender
patent: 5025306 (1991-06-01), Johnson et al.
patent: 5028986 (1991-07-01), Sugano et al.
patent: 5032896 (1991-07-01), Little et al.
patent: 5055425 (1991-10-01), Leibovitz
patent: 5075253 (1991-12-01), Sliwa, Jr.
patent: 5093708 (1992-03-01), Solomon
patent: 5104820 (1992-04-01), Go et al.
patent: 5111278 (1992-05-01), Eichelberger
patent: 5117282 (1992-05-01), Salatino
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5135556 (1992-08-01), Hornback
patent: 5138437 (1992-08-01), Kunamoto et al.
patent: 5138438 (1992-08-01), Masayuki
patent: 5172303 (1992-12-01), Bernardoni
patent: 5191404 (1993-03-01), Wu
patent: 5191405 (1993-03-01), Tomita
patent: 5198888 (1993-03-01), Sugano
patent: 5200300 (1993-04-01), Leibovitz
patent: 5202754 (1993-04-01), Bertin
patent: 5221642 (1993-06-01), Burns
patent: 5222014 (1993-06-01), Lin
patent: 5229647 (1993-07-01), Gnadinger
patent: 5231304 (1993-07-01), Solomon
patent: 5247423 (1993-09-01), Lin et al.
patent: 5259110 (1993-11-01), Bross et al.
patent: 5270261 (1993-12-01), Bertin
patent: 5270571 (1993-12-01), Parks et al.
patent: 5279029 (1994-01-01), Burns
patent: 5283107 (1994-02-01), Bayer et al.
patent: 5311401 (1994-05-01), Gates, Jr. et al.
patent: 5330359 (1994-07-01), Walker
patent: 5377077 (1994-12-01), Burns
patent: 5420751 (1995-05-01), Burns
patent: 5446620 (1995-08-01), Burns et al.
patent: 5455740 (1995-10-01), Burns
patent: 5475920 (1995-12-01), Burns et al.
patent: 5479318 (1995-12-01), Burns
patent: 5493476 (1996-02-01), Burns
patent: 5499160 (1996-03-01), Burns
patent: 5543664 (1996-08-01), Burns
patent: 5550711 (1996-08-01), Burns et al.
patent: 5552963 (1996-09-01), Burns
patent: 5561591 (1996-10-01), Burns
patent: 5566051 (1996-10-01), Burns
Wojnarowski, R.J., et al. "Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Process," IEEE International Conference on Wafer Scale Integration, Jan. 20, 1993.
Conte, AIS. "MCM-LThe Answer for Desktop Workstations," ICEMM Proceedings, (1993), pp. 18-21.
Sautter Kenneth M.
Vindasius Alfons
Cubic Memory Inc.
Niebling John F.
Zarneke David A.
LandOfFree
Method for forming vertical interconnect process for silicon seg does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming vertical interconnect process for silicon seg, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming vertical interconnect process for silicon seg will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1371008