Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-04-08
1998-05-26
Fourson, George R.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438427, 438433, 438702, H01L 2176
Patent
active
057563896
ABSTRACT:
A semiconductor device isolating method is disclosed which may include the steps of: forming a buffer layer and an insulating layer on a semiconductor substrate, and etching to remove partially the insulating layer so as to form an opening corresponding to the device isolating region; forming hemispherical polysilicon patterns on the whole surface of the substrate; removing the buffer layer exposed between the HSG-Si patterns on the bottom of the opening, and dry-etching the resultant exposed silicon regions to form a plurality of trenches and silicon poles with a certain depth and length; forming an oxide layer on the inside of the trench, and filling the interior of the trench with polysilicon; and oxidizing the polysilicon filled in the trench to form a device isolating region.
REFERENCES:
patent: 5308786 (1994-05-01), Lar et al.
patent: 5374583 (1994-12-01), Lar et al.
patent: 5393373 (1995-02-01), Jan et al.
Wolf, S. Silicon Processing for the VLSI Era: vol. 2, Process Integration, Lattice Press, 1990, pp. 56-57.
J.H.Ahn, et al.; "Micro Villus Patterning (MVP) Technology for 256Mb DRAM Stack Cell"; 1992 Symposium on VLSI Technology Digest of Technical Papers; pp. 12-13.
M. Sakao, et al.; "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs"; IEDM 90; pp. 655-658.
M. Yoshimaru, et al.; "Rugged Surface Poly-Si Electrode and Low Temperature Deposited Si.sub.3 N.sub.4 for 64MBit and STC Beyond Dram Cell"; IEDM 90; pp. 659-662.
Hirohito Watanabe, et al.; "Device application and structure obvservation for hemispherical-grained"; J. Appl. Phys., vol. 71, No. 7, 1 Apr. 1992; pp.3538-3543.
Huh Yoon-Jong
Lim Jun-Hee
Fourson George R.
Goldstar Electron Company, Ltd.
LandOfFree
Method for forming trench isolation for semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming trench isolation for semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming trench isolation for semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1959421