Method for forming trench isolation

Details Method for forming trench isolation Method for forming trench isolation

2001-01-19

2003-01-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S223000, C438S424000, C438S524000

Reexamination Certificate

active

06503814

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to manufacturing semiconductors, and more specifically to forming trench isolation for use in semiconductor device.
BACKGROUND OF THE INVENTION
One of the objections in forming transistors is to minimize the leakage that occurs when the transistor is in a non-conductive state. This is important for many applications, especially ones requiring a battery. Common operation of circuits using batteries are for cell phones, pagers and personal digital assistants. There are a very large number of transistors on a typical integrated circuit that is utilized by one of these devices. Even millions of transistors may be required in providing the functions required for such devices. Thus, a very tiny amount of leakage by each transistor can result in significant current drain which has the effect of draining the battery and requiring more frequent recharging of the battery.
One of the problems that transistors have commonly is leakage at the corners, the corner where the isolation and the edge of the gate intersect. This arises most typically because of the rounding of trench isolation. The trench isolation is more etched at boundary between an active region, where the transistor is formed, and the trench isolation. This rounding results in a source of leakage.
In describing this particular problem, reference is made to prior art
FIG. 1
, that shows a device
10
comprising a substrate
12
, a trench isolation region
14
and a photoresist mask
16
. Substrate
12
has a semiconductor material such as silicon at least at the surface. Trench
14
is typically silicon oxide so that photoresist
16
is used as a mask for an implant to form an N-well, so photoresist mask
16
has one boundary over trench
14
. The N-type material is typically phosphorus but may be some other material such as arsenic. Another possibility is that it be a combination of two types of N-type material such as arsenic and phosphorus. In such a combination, the phosphorus is typically the deeper of the two.
Shown in
FIG. 2
is an analogous operation for forming a P-well. Device has a photoresist region
18
overlying N-well
20
which was formed as a result of the implant shown in FIG.
1
. Shown in
FIG. 2
is a P-type implant to form a P-well. The result of this implant is shown in FIG.
3
. The trench region
14
is shown as having two doped regions
22
and
24
and P-well
26
along with previously formed N-well. The P-type doping is typically boron, and with the N-type doping being typically phosphorous, a portion of trench
14
is phosphorous doped and a portion is boron doped. Trench region
14
does extend above a surface
28
of substrate
10
. This arises because of the nitride which is used as a mask for forming the trench. After trench
14
is etched out of substrate
12
, there is a subsequent oxide fill of the trench, a CMP process to planarize, and a subsequent removal of the nitride. Thus, the resulting trench fill protrudes above surface
28
.
This protruding region must be reduced and desirably result in a level which is the same as that of surface
28
. After such an etch to reduce the protrusion, the result is shown in FIG.
4
. The result is that region
24
is lower than boron doped region
22
. This is an undesirable result of the phosphorous-doped oxide. In this case, region
24
etches faster than the boron-doped oxide of region
22
. After etching trench region
14
, an oxide layer
30
is formed on surface
28
of substrate
12
. After oxide layer
30
has been formed, polysilicon is deposited and selectively removed to leave polysilicon region
32
over N-well
20
and polysilicon region
34
over P-well
26
. Polysilicon region
32
extends over trench
14
and more specifically, phosphorous-doped region
24
. Similarly, polysilicon region
34
extends over trench region
14
and particularly over boron doped region
22
. The resulting structure shown in
FIG. 5
demonstrates the typical problem where leakage occurs.
A region
36
is at an interface between surface
28
and trench region
14
. At this interface
36
, there is a portion of trench
14
which is recessed downward. This recessed downward area is a corner of a transistor of which polysilicon region
32
is a gate. It is in this region
36
where leakage is a primary problem. Notice that the gate, which is formed from polysilicon region
32
, extends downward into trench
14
. This is an area which is different than the other portion of the transistor. This
FIG. 5
cross section shows a channel region
35
between a source and a drain that are not shown in this cross section. The source and drain would be in a cross section taken orthogonal to this cross section. The current drain path that is problematic is through a region such as region
36
, which typically occurs, between the source and drain. Another problem that relates to undesirable leakage is diode leakage between the source/drain regions and the well region. There is thus a need to reduce current leakage which arises as a result of region such as region
36
and diode leakage.


REFERENCES:
patent: 5989978 (1999-11-01), Peidous

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