Method for forming thin tunneling windows in EEPROMs

Details Method for forming thin tunneling windows in EEPROMs Method for forming thin tunneling windows in EEPROMs

1993-07-30

1994-10-04

Fourson, George

Fishing, trapping, and vermin destroying

437238, 437241, 437979, 437985, 148DIG117, 148DIG163, H01L 21265

Patent

active

053526180

ABSTRACT:
A method for making submicron dielectric windows for electron tunneling between a floating gate and substrate in a semiconductor EEPROM device. A mask edge overlying an oxide layer on a substrate is undercut a small distance, the area surrounding that small distance is built up with oxide, then a thin layer of oxide is formed in the undercut distance to serve as a tunneling window.

REFERENCES:
patent: 4755477 (1988-07-01), Chao
patent: 5236862 (1993-08-01), Pfiester et al.
Sung et al., "Reverse L-Shape Sealed Poly-Buffer LOCOS Tech.", IEEE Electron Device Letters, vol. 11, No. 11, pp. 549-551 (1990).
Roth et al., "Characterization of Polysilicon-Encapsulated Local Oxidation", IEEE Transactions on Electron Devices, vol. 39, No. 5, (1992).

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